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  <channel>
    <title>i.MX Processors中的主题 Re: IMX93 u-boot for LPDDR4</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2030685#M233133</link>
    <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/237705"&gt;@logan3c3&lt;/a&gt;!&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;You can use our &lt;A href="https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX" target="_self"&gt;Config Tools for i.MX Applications Processors&lt;/A&gt; to generate your timing file and perform the DDR tests.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 20 Jan 2025 13:19:52 GMT</pubDate>
    <dc:creator>Chavira</dc:creator>
    <dc:date>2025-01-20T13:19:52Z</dc:date>
    <item>
      <title>IMX93 u-boot for LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2029707#M233076</link>
      <description>&lt;P&gt;Hello team,&lt;BR /&gt;i am trying to port u-boot for a custom board with lpddr4 when i added ddr timing file and even modified spl.c by hardcoding ddr timing. The build was successful i made image into a Flash.bin file but i wasn't able to flash the file to the target board emmc the flashing fails after 19% , i checked the cable and the usb port everything is okay and working fine. Is any further changes required to be made to board specific files related to lpddr4 am i missing any steps as i have already modified Kconfig, Makefile,dts and defconfig for the same can anybody help with what i am facing??&amp;nbsp;&amp;nbsp;&lt;BR /&gt;#IMX93evk #u-boot #spl&lt;/P&gt;</description>
      <pubDate>Fri, 17 Jan 2025 10:50:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2029707#M233076</guid>
      <dc:creator>logan3c3</dc:creator>
      <dc:date>2025-01-17T10:50:42Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 u-boot for LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2029792#M233083</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/237705"&gt;@logan3c3&lt;/a&gt;!&lt;/P&gt;
&lt;P&gt;Thank you for contacting NXP Support!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Do you performed the ddr stress test to your board with your timing configuration??&lt;/P&gt;
&lt;P&gt;It is important to configure correctly the ddr memory in your board and when your board pass all the ddr stress test you should not have problems flashing or booting your board.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards!&lt;/P&gt;
&lt;P&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Fri, 17 Jan 2025 13:23:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2029792#M233083</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-01-17T13:23:00Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 u-boot for LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2030076#M233098</link>
      <description>Can you please confirm if the methods i followed are correct. can you please suggest the tool to test stress test for imx93</description>
      <pubDate>Sat, 18 Jan 2025 07:51:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2030076#M233098</guid>
      <dc:creator>logan3c3</dc:creator>
      <dc:date>2025-01-18T07:51:56Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 u-boot for LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2030685#M233133</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/237705"&gt;@logan3c3&lt;/a&gt;!&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;You can use our &lt;A href="https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX" target="_self"&gt;Config Tools for i.MX Applications Processors&lt;/A&gt; to generate your timing file and perform the DDR tests.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 20 Jan 2025 13:19:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2030685#M233133</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-01-20T13:19:52Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 u-boot for LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2031189#M233173</link>
      <description>&lt;P&gt;it passed all the stress test. but still not being able to flash the file to emmc. what might be the issue also while building u-boot gives warning related to bl31.bin not present and u-boot.bin not present which is then later used in building final image "flash.bin"&lt;/P&gt;</description>
      <pubDate>Tue, 21 Jan 2025 07:35:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2031189#M233173</guid>
      <dc:creator>logan3c3</dc:creator>
      <dc:date>2025-01-21T07:35:29Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 u-boot for LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2031316#M233178</link>
      <description>&lt;P&gt;Here are the modifications i have done&lt;BR /&gt;&lt;BR /&gt;added support in &lt;STRONG&gt;arch/arm/mach-imx/imx9/Kconfig&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;config TARGET_IMX93_11X11_EVK
        bool "imx93_11x11_evk"
        select OF_BOARD_FIXUP
        select IMX93

config TARGET_IMX93_CALIXTO_VERSA_256
        bool "imx93_calixto_versa"
        select OF_BOARD_FIXUP
        select IMX93
config TARGET_IMX93_CALIXTO_VERSA_512
        bool "imx93_calixto_versa"
        select OF_BOARD_FIXUP
        select IMX93
config TARGET_IMX93_CALIXTO_VERSA_1024
        bool "imx93_calixto_versa"
        select OF_BOARD_FIXUP
        select IMX93
config TARGET_IMX93_CALIXTO_VERSA_2048
        bool "imx93_calixto_versa"
        select OF_BOARD_FIXUP
        select IMX93&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Then i added a new vendor folder path to keep custom board related info.&lt;BR /&gt;&lt;BR /&gt;inside it i modified the Kconfig, spl&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;if TARGET_IMX93_CALIXTO_VERSA_2048 || TARGET_IMX93_CALIXTO_VERSA_1024 || TARGET_IMX93_CALIXTO_VERSA_512 || TARGET_IMX93_CALIXTO_VERSA_256

config SYS_BOARD
    default "imx93_calixto_versa"

config SYS_VENDOR
    default "calixto"

config SYS_CONFIG_NAME
    default "imx93_calixto_versa"


choice
    prompt "Select DDR Type"
    default IMX93_EVK_LPDDR4 if TARGET_IMX93_CALIXTO_VERSA_2048 || TARGET_IMX93_CALIXTO_VERSA_1024 || TARGET_IMX93_CALIXTO_VERSA_512 || TARGET_IMX93_CALIXTO_VERSA_256
    help
        Select the type of DDR to be used.

config IMX93_EVK_LPDDR4X
    bool "Using LPDDR4X Timing and PMIC voltage"
    select IMX9_LPDDR4X
    help
      Select the LPDDR4X timing and 0.6V VDDQ

config IMX93_EVK_LPDDR4
    bool "Using LPDDR4 Timing and PMIC voltage"
    select IMX9_LPDDR4X
    help
      Select the LPDDR4 timing and 1.1V VDDQ

endchoice

endif&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;For SPL&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;extern struct dram_timing_info dram_timing_1866mts;
extern struct dram_timing_info lpddr4_2GiB_micron_timing;
void spl_dram_init(void)
{
        struct dram_timing_info *ptiming = &amp;amp;lpddr4_2GiB_micron_timing;

#if IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4) &amp;amp;&amp;amp; IS_ENABLED(CONFIG_TARGET_IMX93_CALIXTO_VERSA_2048)
        if (is_voltage_mode(VOLT_LOW_DRIVE))
                ptiming = &amp;amp;lpddr4_2GiB_micron_timing;
#elif IS_ENABLED(CONFIG_TARGET_IMX93_CALIXTO_VERSA_2048) &amp;amp;&amp;amp; IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)
                ptiming = &amp;amp;lpddr4x_2GB_versa_timing;
#elif IS_ENABLED(CONFIG_TARGET_IMX93_CALIXTO_VERSA_1024) &amp;amp;&amp;amp; IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)
                ptiming = &amp;amp;lpddr4x_1GB_versa_timing;
#elif IS_ENABLED(CONFIG_TARGET_IMX93_CALIXTO_VERSA_512) &amp;amp;&amp;amp; IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)
                ptiming = &amp;amp;lpddr4x_512MB_versa_timing;
#elif IS_ENABLED(CONFIG_TARGET_IMX93_CALIXTO_VERSA_256) &amp;amp;&amp;amp; IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)
                ptiming = &amp;amp;lpddr4x_256MB_versa_timing;

#endif

        printf("DDR: %uMTS\n", ptiming-&amp;gt;fsp_msg[0].drate);
        ddr_init(ptiming);
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;and i have copied include file to the custom board name, created dts and defconfig from the reference board.&lt;BR /&gt;&lt;BR /&gt;Do i need to modify anything apart from this??&lt;/P&gt;</description>
      <pubDate>Tue, 21 Jan 2025 08:59:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2031316#M233178</guid>
      <dc:creator>logan3c3</dc:creator>
      <dc:date>2025-01-21T08:59:14Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 u-boot for LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2032392#M233239</link>
      <description>&lt;P&gt;HI &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/237705"&gt;@logan3c3&lt;/a&gt;!&lt;/P&gt;
&lt;P&gt;Have you updated your config for each ddr size?&lt;/P&gt;
&lt;P&gt;The config file for iMX93 EVK is &lt;A href="https://github.com/nxp-imx/uboot-imx/blob/lf_v2022.04/include/configs/imx93_evk.h#L185" target="_self"&gt;this file&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Also you have to update the OPTEE OS configurations too if is used in &lt;A href="https://github.com/nxp-imx/imx-optee-os/blob/e0a3e77735941e6057a1994a576b83a93ea0bdb9/core/arch/arm/plat-imx/conf.mk#L457" target="_self"&gt;this file&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Try updating those files according each model that you want to use it.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We have a similar configuration for LPDDR4 and DDR4 models in iMX8MP EVK you can take as a reference for your implementation that &lt;A href="https://github.com/nxp-imx/uboot-imx/blob/lf_v2022.04/include/configs/imx8mp_evk.h#L213" target="_self"&gt;configuration file&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards!&lt;/P&gt;
&lt;P&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jan 2025 13:39:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2032392#M233239</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-01-22T13:39:49Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 u-boot for LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2032802#M233270</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206761"&gt;@Chavira&lt;/a&gt;&amp;nbsp;,&lt;BR /&gt;Currently i am trying to build only for 2048 so its configured for 2GB but is not being able flash per se . I have not modified for rest of the memory configuration as i am not building those. I am not using OPTEE also. What might be the problem?&lt;/P&gt;</description>
      <pubDate>Thu, 23 Jan 2025 04:16:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2032802#M233270</guid>
      <dc:creator>logan3c3</dc:creator>
      <dc:date>2025-01-23T04:16:22Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 u-boot for LPDDR4</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2033228#M233300</link>
      <description>&lt;P&gt;HI &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/237705"&gt;@logan3c3&lt;/a&gt;!&lt;/P&gt;
&lt;P&gt;Have you download and include the files l&lt;STRONG&gt;pddr4_pmu_train_imem.bin&lt;/STRONG&gt; and &lt;STRONG&gt;lpddr4_pmu_train_dmem.bin&lt;/STRONG&gt;?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Can you share your patches (u-boot, SPL, ATF, etc) and timing files to try by my side?&lt;/P&gt;
&lt;P&gt;Are you compiling with Yocto or Standalone?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I recommend to do that Standalone first.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards!&lt;/P&gt;
&lt;P&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Thu, 23 Jan 2025 14:11:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-u-boot-for-LPDDR4/m-p/2033228#M233300</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-01-23T14:11:28Z</dc:date>
    </item>
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