i.MX ProcessorsのトピックRe: SAI TDM channel offset bug

SAI TDM channel offset bug

inojosh — Tue, 14 Jan 2025 00:33:54 GMT

I have seen some other posts on this subject, but with no solutions or suggestions from NXP.

So, I am bringing it up again.

With SAI setup as TDM, the channels can become unaligned under various circumstances.

For example, with TDM8, you always expect channel 1 to be directly after the FS transition.

But if the BCK/FS clocks are stopped and restarted, the IMX8 will re-arrange the channels in a seemingly random way. For example, everything will be shifted backwards, so channel 1 is in channel 8's slot.

So from a software perspective, we cannot get the expected data because the channels are shifted around.

Another condition that has caused this shift to happen: an xrun on SAI2 (normal I2S) results in channel rearrangement on SAI5 (TDM8). This should not happen, of course.

This all seems to be due to either incorrect SAI or SDMA driver code, or perhaps a combination of both.

Re: SAI TDM channel offset bug

JorgeCas — Tue, 14 Jan 2025 17:36:45 GMT

Hello,

This is defined on device tree:

dai-tdm-slot-tx-mask : Transmit direction slot mask, optional

dai-tdm-slot-rx-mask : Receive direction slot mask, optional

There is a .of_xlate_tdm_slot_mask() to specify an explicit mapping of the channels and the slots. If it's absent the default snd_soc_of_xlate_tdm_slot_mask() will be used to generating the tx and rx masks.

Best regards.

Re: SAI TDM channel offset bug

inojosh — Tue, 14 Jan 2025 17:48:13 GMT

As addressed in other posts on this topic, this isn't really relevant to the bug in question.

I am using TDM8, and all slots are active, so the mask serves no purpose.

The problem is that the channels are re-arranged during runtime, when either of the two things occur (and probably other things, but these are the two I know of):

1. The BCK/FS clocks are stopped and restarted. For example, when the SAI is slave, and the clocks are externally generated by a DSP, etc. In this case the iMX8 driver code does not recognize the resyncing of FS, and the channels are offset within the TDM frame.

2. There is an xrun. In my case, I can see an xrun occuring on a different SAI running I2S results in a channel shift on a SAI running TDM.