After enbale MMU, can only access DDR, can't access any peripheral address space include SCU address

luoqiaofa1 — Thu, 02 Jan 2025 03:48:10 GMT

Hello Supports:
I'm trying to run bare AMP software on CPU3 of imx6quard CPU, cpu0-cpu2 run linux 6.1.1
before enable MMU enabled, we can read and write SCU address space(base:0x00a00000)
but after MMU enabled, software can't access any address space except DDR(0x10000000~0x4fffffff), if software do peripheral read access, all system hung up.
what's wrong with me?
I'm sure the MMU take effect, because some address area shared with linux for communication, if them memory attributes is not correct, linux side software can't get the data correctly. I don't known what's wrong happened? need your help

please refer to the attach for the MMU configuration,

I want to use the arm core private timer , so process blocked here.
the amp(cpu3 software print info as follows---don't access the peripheral address)
[-CPU3-]:main-(00065)]Build Time:Jan 2 2025-10:58:55.
[-CPU3-]:main-(00066)]float test pi = 0.000000
[-CPU3-]:main-(00067)]CPU1 process debug addr:0x48029e60
[-CPU3-]:main-(00070)]cpsr reg = 0x400001d3
[-CPU3-]:main-(00072)]vbar reg = 0x48000440
[-CPU3-]:disp_scu_all_regs-(00037)]CBAR_REG = 0x00a00000
[-CPU3-]:disp_scu_all_regs-(00039)]SCU_Control_Register = 0x0000007f
[-CPU3-]:disp_scu_all_regs-(00041)]SCU_Configuration_Register = 0x00005573
[-CPU3-]:disp_scu_all_regs-(00043)]SCU_CPU_Power_Status_Register = 0x00000000
[-CPU3-]:disp_scu_all_regs-(00046)]SCU_Invalidate_All_Registers_in_Secure_State = 0x00000000
[-CPU3-]:disp_scu_all_regs-(00048)]Filtering_Start_Address_Register = 0x00000000
[-CPU3-]:disp_scu_all_regs-(00050)]Filtering_End_Address_Register = 0x00000000
[-CPU3-]:disp_scu_all_regs-(00052)]SCU_Access_Control_Register = 0x0000000f
[-CPU3-]:disp_scu_all_regs-(00054)]SCU_Non-secure_Access_Control_Register = 0x00000000
[-CPU3-]:disp_private_timer_regs-(00076)]CBAR_REG = 0x00a00000
[-CPU3-]:disp_private_timer_regs-(00079)]TWD_TIMER_LOAD= 0x003c6cc0
[-CPU3-]:disp_private_timer_regs-(00081)]TWD_TIMER_COUNTER= 0x003698a9
[-CPU3-]:disp_private_timer_regs-(00083)]TWD_TIMER_CONTROL= 0x00000003
[-CPU3-]:disp_private_timer_regs-(00076)]CBAR_REG = 0x00a00000
[-CPU3-]:disp_private_timer_regs-(00079)]TWD_TIMER_LOAD= 0x003c6cc0
[-CPU3-]:disp_private_timer_regs-(00081)]TWD_TIMER_COUNTER= 0x002a9d89
[-CPU3-]:disp_private_timer_regs-(00083)]TWD_TIMER_CONTROL= 0x00000003
[-CPU3-]:mmu_table_init-(00198)]translation table init done
[-CPU3-]:main-(00065)]Build Time:Jan 2 2025-10:58:55.
[-CPU3-]:main-(00066)]float test pi = 0.000000
[-CPU3-]:main-(00067)]CPU1 process debug addr:0x48029e60
[-CPU3-]:main-(00070)]cpsr reg = 0x400001d3
[-CPU3-]:main-(00072)]vbar reg = 0x48000440
[-CPU3-]:disp_scu_all_regs-(00037)]CBAR_REG = 0x00a00000
[-CPU3-]:disp_scu_all_regs-(00039)]SCU_Control_Register = 0x0000007f
[-CPU3-]:disp_scu_all_regs-(00041)]SCU_Configuration_Register = 0x00005573
[-CPU3-]:disp_scu_all_regs-(00043)]SCU_CPU_Power_Status_Register = 0x00000000
[-CPU3-]:disp_scu_all_regs-(00046)]SCU_Invalidate_All_Registers_in_Secure_State = 0x00000000
[-CPU3-]:disp_scu_all_regs-(00048)]Filtering_Start_Address_Register = 0x00000000
[-CPU3-]:disp_scu_all_regs-(00050)]Filtering_End_Address_Register = 0x00000000
[-CPU3-]:disp_scu_all_regs-(00052)]SCU_Access_Control_Register = 0x0000000f
[-CPU3-]:disp_scu_all_regs-(00054)]SCU_Non-secure_Access_Control_Register = 0x00000000
[-CPU3-]:disp_private_timer_regs-(00076)]CBAR_REG = 0x00a00000
[-CPU3-]:disp_private_timer_regs-(00079)]TWD_TIMER_LOAD= 0x003c6cc0
[-CPU3-]:disp_private_timer_regs-(00081)]TWD_TIMER_COUNTER= 0x0036c697
[-CPU3-]:disp_private_timer_regs-(00083)]TWD_TIMER_CONTROL= 0x00000003
[-CPU3-]:disp_private_timer_regs-(00076)]CBAR_REG = 0x00a00000
[-CPU3-]:disp_private_timer_regs-(00079)]TWD_TIMER_LOAD= 0x003c6cc0
[-CPU3-]:disp_private_timer_regs-(00081)]TWD_TIMER_COUNTER= 0x002b0db6
[-CPU3-]:disp_private_timer_regs-(00083)]TWD_TIMER_CONTROL= 0x00000003

回复： After enbale MMU, can only access DDR, can't access any peripheral address space include SCU add

luoqiaofa1 — Thu, 02 Jan 2025 03:55:59 GMT

after enabled MMU enabled:
[-CPU3-]:mmu_table_init-(00198)]translation table init done
[-CPU3-]:mmu_init-(00265)]ttbr=0x4802c05b
[-CPU3-]:Test_VirtualMMU-(00222)]L1_TblAddr = 0x4802c000
[-CPU3-]:Test_VirtualMMU-(00230)]L1_DescriptorAddr = 0x4802f7a8,L1_Descriptor = 0x483aa9e1
[-CPU3-]:Test_VirtualMMU-(00232)]L1_Descriptor = 0x483aa9e1
[-CPU3-]:Test_VirtualMMU-(00237)]L2_TableBaseAddr = 0x483aa800,L2_DescriptorAddr = 0x483aab6c,L2_Descriptor = 0xdeadb576
[-CPU3-]:Test_VirtualMMU-(00240)]L2_Descriptor = 0xdeadb576
[-CPU3-]:Test_VirtualMMU-(00245)]va = 0xdeadbeef,pa = 0xdeadbeef
[-CPU3-]:main-(00104)]SCU_BASE=0x00a00000
[-CPU3-]:main-(00106)]Enable MMU
[-CPU3-]:disp_cp15_regs-(00104)]MIDR= 0x412fc09a
[-CPU3-]:disp_cp15_regs-(00106)]REVIDR=0x412fc09a
[-CPU3-]:disp_cp15_regs-(00108)]SCTRL= 0x10c5387d
[-CPU3-]:disp_cp15_regs-(00110)]DACR= 0x55555555
[-CPU3-]:disp_cp15_regs-(00112)]ACTLR= 0x00000047
[-CPU3-]:disp_cp15_regs-(00114)]CPACR= 0x00f00000
[-CPU3-]:disp_cp15_regs-(00116)]NSACR= 0x00000000
[-CPU3-]:main-(00113)]Enable SIMD VFP
[-CPU3-]:main-(00115)]Neon Test ...
I: 7298-Q: -8657|I: 28513-Q: 7192|I:-14294-Q: 4935|I: 3797-Q: 25403|I:-13302-Q: 18999|I: 17846-Q:-31606|I: 3377-Q: -1452|I: 690-Q: 10603|I: -2352-Q:-20951|I:-24549-Q: 521|I: 8485-Q: 2026|I:-10757-Q: 30099|I: 5764-Q: 1393|I: -1091-Q: 5758|I:
[-CPU3-]:TestNeon-(00059)]C Intrinsics done
I: 7298-Q: -8657|I: 28513-Q: 7192|I:-14294-Q: 4935|I: 3797-Q: 25403|I:-13302-Q: 18999|I: 17846-Q:-31606|I: 3377-Q: -1452|I: 690-Q: 10603|I: -2352-Q:-20951|I:-24549-Q: 521|I: 8485-Q: 2026|I:-10757-Q: 30099|I: 5764-Q: 1393|I: -1091-Q: 5758|I:
[-CPU3-]:TestNeon-(00095)]NEON Intrinsics done
[-CPU3-]:TestNeon-(00096)]int convert to short test
[-CPU3-]:TestNeon-(00097)]RAW Data:
25791 531569 -2334455 -11515
[-CPU3-]:TestNeon-(00103)]C:
25791 7281 24841 -11515
[-CPU3-]:TestNeon-(00110)]NEON:
25791 7281 24841 -11515
[-CPU3-]:TestNeon-(00118)]NEON saturated:
25791 32767 -32768 -11515
[-CPU3-]:main-(00117)]Normal Distribution Random number Test ...

topic After enbale MMU, can only access DDR, can't access any peripheral address space include SCU address in i.MX Processors

After enbale MMU, can only access DDR, can't access any peripheral address space include SCU address

回复： After enbale MMU, can only access DDR, can't access any peripheral address space include SCU add