i.MX Processors中的主题 Re: Mismatch between TIMING_CFG_2 and MR2

Mismatch between TIMING_CFG_2 and MR2

jekim — Sat, 21 Dec 2024 03:31:50 GMT

Hello,

I generated lpddr4x_timing.c file with configtool for imx93evk. I found the RD_TO_PRE of TIMING_CFG_2 is not matched with the nRTP of lpddr4x MR2. RD_TO_PRE is 15 and nRTP of MR2 is 14. What's the reason of this mismatch made by the configtool?

If the RD_TO_PRE is longer than the actual memory nRTP(auto precharge timing), do following commands also have the delay of one cycle?

Does RD_TO_PRE parameter have the same effect on both lpddr4x and lpddr4?

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Mon, 23 Dec 2024 06:32:41 GMT

Hi @jekim

There are two different timing parameters,TIMING_CFG_2 is from SOM to DDRC, MR2 is from DDRC to DDR Phy.

B.R

Re: Mismatch between TIMING_CFG_2 and MR2

jekim — Mon, 23 Dec 2024 08:10:28 GMT

Hi @pengyong_zhang ,

Is the any reason to use longer 15 for RD_TO_PRE while MR2 nRTP is 14?

I saw a lpddr4x sample which is failing with the mismatch while pass with the aligned 14. What does this result imply?

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Tue, 24 Dec 2024 01:49:55 GMT

HI @jekim

Sorry about misunderstand your question, But i have not found the nRTP of MR2. MR2 only have RL WL WLS and WR LEV, Do not have nRTP. Could you put the picture about it?

B.R

Re: Mismatch between TIMING_CFG_2 and MR2

jekim — Tue, 24 Dec 2024 08:08:56 GMT

Hi @pengyong_zhang ,

Please refer to the below image.

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Wed, 25 Dec 2024 06:34:43 GMT

Hi @jekim

Thanks for your picture, i have talked with our DRAM internal team, This is because our DDRC IP error, it can not be set 14, So we use the 15 value, Although it does not match the value of the MR2 register, it does not significantly affect the performance of DDR.

B.R

Re: Mismatch between TIMING_CFG_2 and MR2

jekim — Wed, 25 Dec 2024 07:13:40 GMT

Hi @pengyong_zhang ,

As I mentioned before, I saw one failing lpddr4x sample with RD_TO_PRE 15. It becomes PASS when I change RD_TO_PRE from 15 to 14. I need to the exact meaning. I found the latest manual changed the definition as below. nRTP is read auto-precharge related while tRTP is not. Does same RD_TO_PRE setting make the different effect on LPDDR4 and LPDDR4X?

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Wed, 25 Dec 2024 07:56:14 GMT

HI @jekim

As I mentioned before, I saw one failing lpddr4x sample with RD_TO_PRE 15

>>> Could you please tell more about this fail LPDDR4X sample? What test did you run or anything other situation?

Does same RD_TO_PRE setting make the different effect on LPDDR4 and LPDDR4X?

>>> As i know, LPDDR4 and LPDDR4X only the VDDQ is different, So i think same RD_TO_PRE setting make no different effect on LPDDR4 and LPDDR4X.

B.R

Re: Mismatch between TIMING_CFG_2 and MR2

jekim — Wed, 25 Dec 2024 08:14:55 GMT

Hi @pengyong_zhang ,

As I mentioned before, I saw one failing lpddr4x sample with RD_TO_PRE 15

>>> Could you please tell more about this fail LPDDR4X sample? What test did you run or anything other situation?

<<< the lpddr4x sample was failed with memtester.

Does same RD_TO_PRE setting make the different effect on LPDDR4 and LPDDR4X?

>>> As i know, LPDDR4 and LPDDR4X only the VDDQ is different, So i think same RD_TO_PRE setting make no different effect on LPDDR4 and LPDDR4X.

<<< then, what's the reason of the imx93 reference manual shows different definition between LPDDR4 and LPDDR4x?

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Wed, 25 Dec 2024 09:37:52 GMT

HI @jekim

Please lower the DDR frequency and try RD_TO_PRE 15 again.

B.R

Re: Mismatch between TIMING_CFG_2 and MR2

jekim — Thu, 26 Dec 2024 00:51:09 GMT

Hi @pengyong_zhang ,

I will try it but could you please answer about the different RD_TO_PRE definition between LPDDR4 and LPDDR4X?

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Thu, 26 Dec 2024 01:34:42 GMT

HI @jekim

There is no different about RD_TO_PRE definition between LPDDR4 and LPDDR4X, It is the RM error, i have told the DDR internal team, I think they will fix it in the next RM version.

B.R

Re: Mismatch between TIMING_CFG_2 and MR2

jekim — Fri, 27 Dec 2024 06:31:00 GMT

Hi @pengyong_zhang ,

Thank you for the clarification. The ConfigTool sets MR2 nRTP 12 and RD_TO_PRE 15 at the slower speed 1600MHz. The lpddr4x sample is not failing at the slower speed. I want to know what happens when RD_TO_PRE is 15 at 1866MHz. Could you let me know how the memory access is changed when the RD_TO_PRE is changed from 14 to 15?

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Mon, 30 Dec 2024 01:28:41 GMT

Hi @jekim

When RD_TO_PRE changes from 14 to 15, the DDRC will be delayed by one or two clock cycles after the DRAM is precharge.

B.R

Re: Mismatch between TIMING_CFG_2 and MR2

jekim — Mon, 30 Dec 2024 08:30:25 GMT

Hi @pengyong_zhang ,

If every following memory accesses were delayed evenly from the expected precharge, it has no reason to make the sample failed at RD_TO_PRE 15 while pass at RD_TO_PRE 14. I assume the following active command is delayed but the following read command is not delayed.

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Mon, 30 Dec 2024 08:55:24 GMT

HI @jekim

You are right. So it is strange at RD_TO_PRE 15, your memtester is failed. Could you please tell me more details about your test？Include test command and each test steps, maybe i can try reproduce your case on my site.

PS : you are using our NXP i.mx93 EVK board?

B.R

Re: Mismatch between TIMING_CFG_2 and MR2

jekim — Mon, 30 Dec 2024 09:10:51 GMT

Hi @pengyong_zhang ,

Yes. I'm using the NXP iMX93 EVK with the public memtester software.

memtester version 4

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Tue, 31 Dec 2024 01:29:31 GMT

HI @jekim

What is your mem test code? And what is your failed log ? Because, in our i.MX93 EVK board we have not found any error when we run the memtester.

B.R

Re: Mismatch between TIMING_CFG_2 and MR2

jekim — Tue, 31 Dec 2024 08:17:31 GMT

Hi @pengyong_zhang ,

I saw the failure from an engineering sample. So, it wouldn't be seen easily from everywhere. The failure log showed different single bits every time. btw, the mismatch happens from the configtool v16. where can I see the change history?

Thanks.

Re: Mismatch between TIMING_CFG_2 and MR2

pengyong_zhang — Tue, 31 Dec 2024 09:12:59 GMT

Hi @jekim

Please use our latest Config Tool v16.1 and test again.

https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX

B.R