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    <title>topic Re: IMX8MP ECSPI max transmit size in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ECSPI-max-transmit-size/m-p/2015410#M232103</link>
    <description>&lt;UL&gt;&lt;LI&gt;&lt;SPAN&gt;It is mentioned&amp;nbsp;32-bit wide by 64-entry FIFO for both transmit and receive data.&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;Yes, FIFO is 32*64/8 = 256 bytes long.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Max "burst length" (see CONNREG register) is 4096 bits (512 bytes). That's the max transfer size, eCSPI may toggle CS pin for you automatically on start and end of transfer.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;256 bytes limit you hit perhaps is caused by SW implementation. It must be easier to just fill FIFO and send. 512 bytes would need to use interrupts / flags polling loop / DMA to fill FIFO with&amp;nbsp; what doesn't fit FIFO.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 17 Dec 2024 15:28:32 GMT</pubDate>
    <dc:creator>kef2</dc:creator>
    <dc:date>2024-12-17T15:28:32Z</dc:date>
    <item>
      <title>IMX8MP ECSPI max transmit size</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ECSPI-max-transmit-size/m-p/2014910#M232063</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;I am using ECSPI for user space application. While transmitting data using&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;struct spi_ioc_transfer,&amp;nbsp;&lt;/STRONG&gt;&lt;SPAN&gt;mentioned &lt;/SPAN&gt;&lt;STRONG&gt;.len&lt;/STRONG&gt;&lt;SPAN&gt; as 4096 and its giving error like message to long, bad address.&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;For small .len like 255, it is working fine.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I have checked the reference manual ECSPI features (attached below). It is mentioned&amp;nbsp;32-bit wide by 64-entry FIFO for both transmit and receive data.&lt;/P&gt;&lt;P&gt;Is the max len supported by ECSPI is 256 bytes while transmitting? Does this length can be increased to 65535?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards,&lt;/P&gt;&lt;P&gt;Kartheek&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 17 Dec 2024 05:14:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ECSPI-max-transmit-size/m-p/2014910#M232063</guid>
      <dc:creator>kartheek</dc:creator>
      <dc:date>2024-12-17T05:14:08Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MP ECSPI max transmit size</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ECSPI-max-transmit-size/m-p/2015410#M232103</link>
      <description>&lt;UL&gt;&lt;LI&gt;&lt;SPAN&gt;It is mentioned&amp;nbsp;32-bit wide by 64-entry FIFO for both transmit and receive data.&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;Yes, FIFO is 32*64/8 = 256 bytes long.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Max "burst length" (see CONNREG register) is 4096 bits (512 bytes). That's the max transfer size, eCSPI may toggle CS pin for you automatically on start and end of transfer.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;256 bytes limit you hit perhaps is caused by SW implementation. It must be easier to just fill FIFO and send. 512 bytes would need to use interrupts / flags polling loop / DMA to fill FIFO with&amp;nbsp; what doesn't fit FIFO.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 17 Dec 2024 15:28:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ECSPI-max-transmit-size/m-p/2015410#M232103</guid>
      <dc:creator>kef2</dc:creator>
      <dc:date>2024-12-17T15:28:32Z</dc:date>
    </item>
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