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    <title>i.MX ProcessorsのトピックRe: iMX8MP OCRAM (map, uses)</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-OCRAM-map-uses/m-p/2010824#M231777</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;About unable to use full OCRAM memory size (576KB), please use below link for detailed info:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/How-to-access-to-the-top-address-of-OCRAM-for-i-MX8QXP/m-p/1068709/highlight/true" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/How-to-access-to-the-top-address-of-OCRAM-for-i-MX8QXP/m-p/1068709/highlight/true&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Unable-to-access-complete-OCRAM-in-i-mx8mm/td-p/1813513" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Unable-to-access-complete-OCRAM-in-i-mx8mm/td-p/1813513&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Due to ATF partition, that also the reason why the DTS definition at &amp;lt;imx8mp.dtsi&amp;gt; not set OCRAM size to 576KB.&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;ocram: ocram@900000 {
			no-map;
			reg = &amp;lt;0 0x900000 0 0x70000&amp;gt;;
		};&lt;/LI-CODE&gt;
&lt;P&gt;Customer can modify above OCRAM memory size to 512KB (0x80000) and leave 64KB for ATF usage.&lt;/P&gt;
&lt;P&gt;Thanks for the attention.&lt;/P&gt;
&lt;P&gt;Mike&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 10 Dec 2024 08:05:41 GMT</pubDate>
    <dc:creator>Hui_Ma</dc:creator>
    <dc:date>2024-12-10T08:05:41Z</dc:date>
    <item>
      <title>iMX8MP OCRAM (map, uses)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-OCRAM-map-uses/m-p/2009028#M231654</link>
      <description>&lt;P&gt;Hi, colleagues and NXP engineers!&lt;/P&gt;&lt;P&gt;I have some questions on iMX8MP, the topic is OCRAM.&lt;BR /&gt;It's claimed it has 576kB of OCRAM &lt;SPAN class=""&gt;—&lt;/SPAN&gt; p.25, section "2.2 Cortex-A53 Memory Map".&lt;BR /&gt;According to this section OCRAM starts from 900000h and goes up to 98FFFFh.&lt;BR /&gt;This range represents the claimed 576kBs. At this point, everything is clear.&lt;/P&gt;&lt;P&gt;Also, there is memory for BootROM (or iROM, maybe?), which is described on p.26&lt;BR /&gt;of the same section. Its range is from zeroes to 3FFFFh &lt;SPAN class=""&gt;—&lt;/SPAN&gt; which represents 256kB.&lt;/P&gt;&lt;P&gt;But there is "Figure 6-2. Internal ROM and RAM memory map" on p.748, which&lt;BR /&gt;leads to confusion. The left side remains clear because it doesn't conflict&lt;BR /&gt;with p.26. But the right side "OCRAM Memory Map" is unclear to me.&lt;/P&gt;&lt;P&gt;The first question is &lt;SPAN class=""&gt;—&lt;/SPAN&gt; why OCRAM top is lower by 10000h on p.748 compared to p.25?&lt;/P&gt;&lt;P&gt;I've done some research which lead to few more questions.&lt;BR /&gt;Second question. Let's assume iROM can't place application in 900000h because&lt;BR /&gt;at that moment it uses that memory region. But why I can't place my application&lt;BR /&gt;at 918000h (as shown in the table)? It can run only being placed at 920000h and&lt;BR /&gt;higher. Otherwise, it hangs.&lt;/P&gt;&lt;P&gt;I've done some kind of memory test by setting SP to specific locations and using&lt;BR /&gt;reentrant function which outputs SP and calls itself.&lt;/P&gt;&lt;P&gt;If I set SP to the same 920000h it goes all the way down to the (almost) 900000h.&lt;BR /&gt;This behavior can be explained &lt;SPAN class=""&gt;—&lt;/SPAN&gt; I just rewrite the "Reserved for ROM" region and&lt;BR /&gt;reach the bottom of memory. This is allowed because the CPU is not in iROM at&lt;BR /&gt;that moment, and it is said: "If no ROM/HAB APIs are being used, the entire OCRAM&lt;BR /&gt;region can be used freely after the boot." (p.748)&lt;/P&gt;&lt;P&gt;When I set SP to 990000h (which is 576kB boundary) it goes all the way down until&lt;BR /&gt;it meets my code, which in that case was placed at "standard" 920000h and is about&lt;BR /&gt;1.5kB in size. At that moment it crashes because it's destroyed. That looks clear too.&lt;/P&gt;&lt;P&gt;But the highest top position I could place my application to &lt;SPAN class=""&gt;—&lt;/SPAN&gt; is 970000h (the size&lt;BR /&gt;of my binary still was ~1.5kB). That is not clear to me. Possibly it can be explained&lt;BR /&gt;by assuming that iROM (by some reason) doesn't allow loading application at&lt;BR /&gt;addresses higher than 970000h. But why?&lt;/P&gt;&lt;P&gt;Third question. In addition to all that, I've noticed OCRAM region in Linux is set like&lt;BR /&gt;this:&lt;/P&gt;&lt;P&gt;ocram: ocram@900000 {&lt;BR /&gt;no-map;&lt;BR /&gt;reg = &amp;lt;0 0x900000 0 0x70000&amp;gt;;&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;its size is 70000h! Which is 448kB. And it is DTS for&amp;nbsp;iMX8MP exactly (!) &lt;SPAN class=""&gt;—&lt;/SPAN&gt; not the 8th,&lt;BR /&gt;8M or any other bunch of series.&lt;/P&gt;&lt;P&gt;Thus, we have:&lt;BR /&gt;1. It looks there is mismatch in OCRAM specification in different datasheet sections.&lt;BR /&gt;2. It looks the memory on the top is usable but at runtime only, application and/or&lt;BR /&gt;its data can't be placed there.&lt;BR /&gt;3. Also, application should be placed with some offset higher than claimed in OCRAM&lt;BR /&gt;Memory Map.&lt;BR /&gt;4. Unclear OCRAM Linux kernel OF Node.&lt;/P&gt;&lt;P&gt;After all, my guess is &lt;SPAN class=""&gt;—&lt;/SPAN&gt; iROM doesn't load application to specific addresses (controls&lt;BR /&gt;allowed/not allowed addresses to load and place application to). But this is not&lt;BR /&gt;documented and does not explain why these and those addresses are not allowed and&lt;BR /&gt;does not explain kernel's OF node describing OCRAM.&lt;/P&gt;&lt;P&gt;Could someone please clarify or explain the actual iMX8MP OCRAM map and use of it?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="p.25 — 2.2 Cortex-A53 Memory Map" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/314515iD005E13780394EE4/image-size/large?v=v2&amp;amp;px=999" role="button" title="p.25 (2.2 Cortex-A53 Memory Map).png" alt="p.25 — 2.2 Cortex-A53 Memory Map" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;p.25 — 2.2 Cortex-A53 Memory Map&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="p.26 — 2.2 Cortex-A53 Memory Map" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/314516i2F7FC77741830137/image-size/large?v=v2&amp;amp;px=999" role="button" title="p.26 (2.2 Cortex-A53 Memory Map).png" alt="p.26 — 2.2 Cortex-A53 Memory Map" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;p.26 — 2.2 Cortex-A53 Memory Map&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="p.748 — 6.1.4.1 Internal ROM/RAM memory map" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/314517i9C465FDD21819092/image-size/large?v=v2&amp;amp;px=999" role="button" title="p.748 (6.1.4.1 Internal ROM-RAM memory map).png" alt="p.748 — 6.1.4.1 Internal ROM/RAM memory map" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;p.748 — 6.1.4.1 Internal ROM/RAM memory map&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 06 Dec 2024 09:53:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-OCRAM-map-uses/m-p/2009028#M231654</guid>
      <dc:creator>Timofey</dc:creator>
      <dc:date>2024-12-06T09:53:52Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8MP OCRAM (map, uses)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-OCRAM-map-uses/m-p/2010824#M231777</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;About unable to use full OCRAM memory size (576KB), please use below link for detailed info:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/How-to-access-to-the-top-address-of-OCRAM-for-i-MX8QXP/m-p/1068709/highlight/true" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/How-to-access-to-the-top-address-of-OCRAM-for-i-MX8QXP/m-p/1068709/highlight/true&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Unable-to-access-complete-OCRAM-in-i-mx8mm/td-p/1813513" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Unable-to-access-complete-OCRAM-in-i-mx8mm/td-p/1813513&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Due to ATF partition, that also the reason why the DTS definition at &amp;lt;imx8mp.dtsi&amp;gt; not set OCRAM size to 576KB.&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;ocram: ocram@900000 {
			no-map;
			reg = &amp;lt;0 0x900000 0 0x70000&amp;gt;;
		};&lt;/LI-CODE&gt;
&lt;P&gt;Customer can modify above OCRAM memory size to 512KB (0x80000) and leave 64KB for ATF usage.&lt;/P&gt;
&lt;P&gt;Thanks for the attention.&lt;/P&gt;
&lt;P&gt;Mike&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 10 Dec 2024 08:05:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-OCRAM-map-uses/m-p/2010824#M231777</guid>
      <dc:creator>Hui_Ma</dc:creator>
      <dc:date>2024-12-10T08:05:41Z</dc:date>
    </item>
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