i.MX Processorsのトピックi.MX93 ENET QOS MII mode

i.MX93 ENET QOS MII mode

PBoerner — Tue, 03 Dec 2024 12:19:52 GMT

In i.MX93 Applications Processor Reference Manual it's stated that only RMII and RGMII PHYs are supported. But also at several places the manual talks about MII mode. For example in chapter "78.4.1.7 ENET QOS control signals" bits 1-3 can be used to set MII mode.

So they question is, is there a possibility to really set the MII mode and if so, what about the related IO pins and what else has to be set.

Re: i.MX93 ENET QOS MII mode

JosephAtNXP — Tue, 03 Dec 2024 21:42:51 GMT

Hi,

Thank you for your interest in NXP Semiconductor products,

According to the following driver, the PHY-MODE property set to MII is a valid case for an i.MX 93 EQoS configuration. It should be supported on the module.

https://github.com/nxp-imx/linux-imx/blob/e0f9e2afd4cff3f02d71891244b4aa5899dfc786/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c#L152-L176

Regards

Re: i.MX93 ENET QOS MII mode

PBoerner — Wed, 04 Dec 2024 07:16:49 GMT

Thanks for the clarification. It looks like the same support is currently not implemented in U-Boot. So I can use MII only after kernel has started.

Do you have any hints to the right device-tree settings?

Re: i.MX93 ENET QOS MII mode

PBoerner — Wed, 04 Dec 2024 14:06:32 GMT

Trying MII mode by setting phy-mode in the device-tree for eqos o mii leads to an error

stmmac_hw_setup: DMA engine initialization failed.

And the driver initialization stops.

Any idea why this happens for MII mode?

Re: i.MX93 ENET QOS MII mode

PBoerner — Thu, 05 Dec 2024 15:04:45 GMT

Ignoring the DMA initialization error the driver starts.

But the problem now is the TX clock. The RGMII_TX_CLK is connected to the TX clock output of the PHY. So both pins are acting as an output and driving against each other.

I used the same approach as for RMII and modified the part in imx93_set_intf_mode in dwmac-imx.c so the register 2C in GPR is set to 0. According to the manual TX_CLK of ENET QOS should now be an output. But measuring the signals at the pins shows that the i.MX93 is still driving against the output from the PHY.

So the question is, how can the TX_CLK pin be configured as an input for the TX clock signal for MII mode?

Re: i.MX93 ENET QOS MII mode

JosephAtNXP — Tue, 10 Dec 2024 05:48:28 GMT

Hi,

They cannot, TX_CLK should be connected to TX_CLK of the PHY (this pin should be an input driven by the MAC) and RX_CLK should be connected to RX_CLK (this clock is driven by the PHY).

You should adjust it in hardware.

Regards,