i.MX Processors中的主题 Re: Pin status for iMX8M plus soc

Pin status for iMX8M plus soc

KalpeshD — Wed, 27 Nov 2024 13:52:38 GMT

Hi Team NXP,

Refer below snapshot of the datasheet.
Highlighted pin status as mentioned. Is this "RESET CONDITION" mean to the status of pins while the SOC is in reset condition(J29 pin_POR is low) or soc reset release condition(J29 pin_POR is high) ??

If this is of during reset condition then what could be the pin status after reset release and till before we configure IO pins to required levels?

Waiting for the clarification for this topic. Thanks.

Re: Pin status for iMX8M plus soc

JosephAtNXP — Thu, 28 Nov 2024 15:36:21 GMT

Hi,

Thank you for your interest in NXP Semiconductor products,

The RESET CONDITION is after POR_B rises.

During reset condition, we couldn't manage the GPIOs nor the status of them. The reset condition assigns a default function to every pin after POR_B rises, so BootROM is executed correctly and the boot pins are ready to be sampled.

This condition means that boot modules are initialized at BootROM level, GPIO wouldn't but USDHC, NAND, FlexSPI, USB, etc.

Regards