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    <title>i.MX ProcessorsのトピックRe: I.MX93 AMBA Documentation</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1992017#M230727</link>
    <description>&lt;P&gt;Correct!&lt;/P&gt;</description>
    <pubDate>Mon, 11 Nov 2024 14:18:05 GMT</pubDate>
    <dc:creator>Bio_TICFSL</dc:creator>
    <dc:date>2024-11-11T14:18:05Z</dc:date>
    <item>
      <title>I.MX93 AMBA Documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1985747#M230349</link>
      <description>&lt;P&gt;We are looking at not using Linux and developing a bare metal/RTOS application on the Cortex A55 cores of the i.MX93.&lt;BR /&gt;I would like to know the details of the Advanced Microcontroller Bus that interconnects the i.MX93 cores and the peripherals. (There does not seem to be any mention of the AMBA in the "i.MX 93 Applications Processor Reference Manual".)&lt;BR /&gt;Do all (M and A) cores have access to all peripherals?&lt;BR /&gt;How is the ABM arbitration configured?&lt;/P&gt;</description>
      <pubDate>Thu, 31 Oct 2024 18:36:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1985747#M230349</guid>
      <dc:creator>dpolic</dc:creator>
      <dc:date>2024-10-31T18:36:42Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX93 AMBA Documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1986295#M230378</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;For i,mx93 it Manages all transactions that use the Arm AMBA 5 AXI interfaces for more information please check it:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://developer.arm.com/Tools%20and%20Software/Arm%20Virtual%20Hardware" target="_blank"&gt;https://developer.arm.com/Tools%20and%20Software/Arm%20Virtual%20Hardware&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
      <pubDate>Fri, 01 Nov 2024 13:52:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1986295#M230378</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2024-11-01T13:52:22Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX93 AMBA Documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1986307#M230383</link>
      <description>&lt;P&gt;Unfortunately, the link that you have provided does not answer my question.&lt;BR /&gt;Is there a software reference manual for the iMX9352 that complements the hardware reference manual?&lt;/P&gt;</description>
      <pubDate>Fri, 01 Nov 2024 14:22:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1986307#M230383</guid>
      <dc:creator>dpolic</dc:creator>
      <dc:date>2024-11-01T14:22:18Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX93 AMBA Documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1986336#M230384</link>
      <description>&lt;P&gt;Hi, No is not in reference manual since its ARM architecture I send you the link, but we do not have anything about it.&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
      <pubDate>Fri, 01 Nov 2024 15:54:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1986336#M230384</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2024-11-01T15:54:03Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX93 AMBA Documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1986420#M230387</link>
      <description>&lt;P&gt;Is it correct to say that the AXI bus interactions are transparent to the software. Any memory mapped addressed peripheral data transfer does not require special "data bus access request - grant - and transfer state of the AXI bus"?&lt;/P&gt;</description>
      <pubDate>Fri, 01 Nov 2024 20:05:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1986420#M230387</guid>
      <dc:creator>dpolic</dc:creator>
      <dc:date>2024-11-01T20:05:51Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX93 AMBA Documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1991143#M230682</link>
      <description>&lt;P&gt;&lt;SPAN&gt;I have not got a reply to this question:&lt;BR /&gt;&lt;BR /&gt;Is it correct to say that the AXI bus interactions are transparent to the software. Any memory mapped addressed peripheral data transfer does not require special "data bus access request - grant - and transfer state of the AXI bus"?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 08 Nov 2024 14:32:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1991143#M230682</guid>
      <dc:creator>dpolic</dc:creator>
      <dc:date>2024-11-08T14:32:22Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX93 AMBA Documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1992017#M230727</link>
      <description>&lt;P&gt;Correct!&lt;/P&gt;</description>
      <pubDate>Mon, 11 Nov 2024 14:18:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX93-AMBA-Documentation/m-p/1992017#M230727</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2024-11-11T14:18:05Z</dc:date>
    </item>
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