https://community.nxp.com/t5/i-MX-Processors/IMX8M-MAX-to-MAC/m-p/1990739#M230654 <P>on imx8mQ, I need to connect MAC to MAC as described in drawing</P><P>&nbsp;</P><P>ETH1, FEC is connected MAC to MAC via RGMII to Marvel switch (without PHY)</P><P>&nbsp;</P><P>please advice what needs to be changed to support this (I assume DTS change in kernel)</P><P><BR /><BR /></P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ilanganor1_1-1731039255027.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/309356iBE823384AA302EF8/image-size/medium?v=v2&amp;px=400" role="button" title="ilanganor1_1-1731039255027.png" alt="ilanganor1_1-1731039255027.png" /></span></P><P>&nbsp;</P> Fri, 08 Nov 2024 04:15:03 GMT ilanganor1 2024-11-08T04:15:03Z https://community.nxp.com/t5/i-MX-Processors/IMX8M-MAX-to-MAC/m-p/1990739#M230654 <P>on imx8mQ, I need to connect MAC to MAC as described in drawing</P><P>&nbsp;</P><P>ETH1, FEC is connected MAC to MAC via RGMII to Marvel switch (without PHY)</P><P>&nbsp;</P><P>please advice what needs to be changed to support this (I assume DTS change in kernel)</P><P><BR /><BR /></P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ilanganor1_1-1731039255027.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/309356iBE823384AA302EF8/image-size/medium?v=v2&amp;px=400" role="button" title="ilanganor1_1-1731039255027.png" alt="ilanganor1_1-1731039255027.png" /></span></P><P>&nbsp;</P> Fri, 08 Nov 2024 04:15:03 GMT https://community.nxp.com/t5/i-MX-Processors/IMX8M-MAX-to-MAC/m-p/1990739#M230654 ilanganor1 2024-11-08T04:15:03Z https://community.nxp.com/t5/i-MX-Processors/IMX8M-MAX-to-MAC/m-p/1992085#M230728 <P>Hi,</P> <P>Thank you for your interest in NXP Semiconductor products,</P> <P>You should refer to the vendor documentation since we have no reference with those switches.</P> <P>I could quickly found <A href="https://community.nxp.com/t5/i-MX-Processors/Device-tree-configuration-for-Imx8M-Plus-with-Ksz9563-ethernet/td-p/1688755" target="_self">these trials</A>, that are directly based on <A href="https://github.com/nxp-imx/linux-imx/blob/d23d64eea5111e1607efcce1d601834fceec92cb/Documentation/devicetree/bindings/net/dsa/microchip%2Cksz.yaml#L23" target="_self">this documentation</A>.</P> <P>You should first try to just add the PHYs in the MDIO bus without adding the Microchip property, as the <A href="https://github.com/nxp-imx/linux-imx/blob/d23d64eea5111e1607efcce1d601834fceec92cb/arch/arm64/boot/dts/freescale/imx93-14x14-evk-sja1105.dts" target="_self">i.MX93-AUTO-EVK does</A>.</P> <P>Regards</P> Mon, 11 Nov 2024 15:51:42 GMT https://community.nxp.com/t5/i-MX-Processors/IMX8M-MAX-to-MAC/m-p/1992085#M230728 JosephAtNXP 2024-11-11T15:51:42Z