https://community.nxp.com/t5/i-MX-Processors/IMX8ULPIEC-SAI-interfase/m-p/1983524#M230217 <P>This is what I needed, thank you!</P> Tue, 29 Oct 2024 06:48:52 GMT Sandroom 2024-10-29T06:48:52Z https://community.nxp.com/t5/i-MX-Processors/IMX8ULPIEC-SAI-interfase/m-p/1978868#M229963 <P>Good day to all.<BR />I have a task of programming SAI interface for i.mx 8 under m-33 core. I figured out that SAI0 and SAI1 are suitable for me, but I can't figure out from the IO Muxing pins I need. Alternative function for I2S?<BR />For example PTA1 witch Output7 function(I2S0_RX_FS)&nbsp;&nbsp;will work as FS for SAI0 with User Defined Protocol?</P> Tue, 22 Oct 2024 06:44:43 GMT https://community.nxp.com/t5/i-MX-Processors/IMX8ULPIEC-SAI-interfase/m-p/1978868#M229963 Sandroom 2024-10-22T06:44:43Z https://community.nxp.com/t5/i-MX-Processors/IMX8ULPIEC-SAI-interfase/m-p/1983192#M230203 <P>Hello&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/242343">@Sandroom</a>&nbsp;</P> <P>I hope you are doing very well.</P> <P>Please refer to the SDK of the i.MX8ULP. You can download it from MCUXpresso SDK.</P> <P>Check the SAI examples under&nbsp;<SPAN>SDK_2_16_000_EVK-MIMX8ULP/boards/evkmimx8ulp/driver_examples/sai/interrupt_transfer.<BR /></SPAN></P> <P>&nbsp;</P> <P><SPAN>There is a File called pin_mux.c.</SPAN></P> <P>&nbsp;</P> <P><SPAN>There are defined the mux odtions for the pads including PTA1.</SPAN></P> <LI-CODE lang="markup">void BOARD_InitPins(void) { /*!&lt; Function assigned for the core: Cortex-M33[cm33] */ IOMUXC_SetPinMux(IOMUXC_PTA0_I2S0_RX_BCLK, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA0_I2S0_RX_BCLK, IOMUXC_PCR_DSE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA1_I2S0_RX_FS, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA1_I2S0_RX_FS, IOMUXC_PCR_DSE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA10_LPUART1_TX, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA10_LPUART1_TX, IOMUXC_PCR_PE_MASK | IOMUXC_PCR_PS_MASK); IOMUXC_SetPinMux(IOMUXC_PTA11_LPUART1_RX, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA11_LPUART1_RX, IOMUXC_PCR_PE_MASK | IOMUXC_PCR_PS_MASK); IOMUXC_SetPinMux(IOMUXC_PTA2_I2S0_RXD0, 0U); IOMUXC_SetPinMux(IOMUXC_PTA4_I2S0_MCLK, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA4_I2S0_MCLK, IOMUXC_PCR_OBE_MASK | IOMUXC_PCR_DSE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA7_I2S0_TXD0, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA7_I2S0_TXD0, IOMUXC_PCR_DSE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA8_PTA8, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA8_PTA8, IOMUXC_PCR_OBE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA9_PTA9, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA9_PTA9, IOMUXC_PCR_OBE_MASK); }</LI-CODE> <P>&nbsp;</P> <P>Best regards,</P> <P>Salas.</P> Mon, 28 Oct 2024 19:20:11 GMT https://community.nxp.com/t5/i-MX-Processors/IMX8ULPIEC-SAI-interfase/m-p/1983192#M230203 Manuel_Salas 2024-10-28T19:20:11Z https://community.nxp.com/t5/i-MX-Processors/IMX8ULPIEC-SAI-interfase/m-p/1983524#M230217 <P>This is what I needed, thank you!</P> Tue, 29 Oct 2024 06:48:52 GMT https://community.nxp.com/t5/i-MX-Processors/IMX8ULPIEC-SAI-interfase/m-p/1983524#M230217 Sandroom 2024-10-29T06:48:52Z