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  <channel>
    <title>topic Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980881#M230089</link>
    <description>&lt;P&gt;I am using DDR3L and am a little bit confused about the VDD_SOC_IN voltage configuration. According to a datasheet, its range is from 1.15V to 1.3V. So,&lt;SPAN&gt;&amp;nbsp;which voltage is suitable for my application?&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 24 Oct 2024 06:18:21 GMT</pubDate>
    <dc:creator>Nikunj_Solanki</dc:creator>
    <dc:date>2024-10-24T06:18:21Z</dc:date>
    <item>
      <title>Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1979782#M230019</link>
      <description>&lt;P&gt;Hi everyone,&lt;/P&gt;&lt;P&gt;I'm designing a schematic based on the NXP imx6ull MCIMX6Y2DVM09AB processor and I'm looking for some help from the NXP community.&lt;/P&gt;&lt;P&gt;Specifically, I'm interested in the following areas:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;STRONG&gt;Power supply scheme:&lt;/STRONG&gt; How many different voltages are required for the imx6ull MCIMX6Y2DVM09AB processor? What are the typical voltage levels and current requirements for each voltage?&lt;/LI&gt;&lt;LI&gt;&lt;STRONG&gt;Power supply sequence:&lt;/STRONG&gt; What is the recommended power supply sequence for the imx6ull MCIMX6Y2DVM09AB processor? Are there any specific timing requirements or considerations?&lt;/LI&gt;&lt;LI&gt;&lt;STRONG&gt;Component selection:&lt;/STRONG&gt; How do I select the right components for the power supply section? What are the key factors, such as voltage regulators, capacitors, and inductors?&lt;/LI&gt;&lt;LI&gt;&lt;STRONG&gt;Schematic design guidelines:&lt;/STRONG&gt; Are there any specific guidelines or best practices for designing a schematic for the imx6ull MCIMX6Y2DVM09AB processor?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;I would greatly appreciate any advice or insights you can provide. I appreciate any help you can provide.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Best regards,&lt;/STRONG&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 23 Oct 2024 05:03:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1979782#M230019</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-23T05:03:39Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1979939#M230027</link>
      <description>&lt;P&gt;You can refer to our reference design and hardware design guide document, and following our datasheet, following the power on/off &lt;SPAN data-slate-fragment="JTVCJTdCJTIydHlwZSUyMiUzQSUyMnBhcmFncmFwaCUyMiUyQyUyMmNoaWxkcmVuJTIyJTNBJTVCJTdCJTIyaWQlMjIlM0ElMjI5VnFubDIzVzVHJTIyJTJDJTIycGFyYUlkeCUyMiUzQTAlMkMlMjJzcmMlMjIlM0ElMjJzZXF1bmNlJTIyJTJDJTIyZHN0JTIyJTNBJTIyJUU1JUJBJThGJUU1JTg4JTk3JTIyJTJDJTIybWV0YWRhdGElMjIlM0ElMjIlMjIlMkMlMjJtZXRhRGF0YSUyMiUzQSU1QiU1RCUyQyUyMnRleHQlMjIlM0ElMjJzZXF1bmNlJTIyJTdEJTVEJTdEJTVE"&gt;sequnce.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN data-slate-fragment="JTVCJTdCJTIydHlwZSUyMiUzQSUyMnBhcmFncmFwaCUyMiUyQyUyMmNoaWxkcmVuJTIyJTNBJTVCJTdCJTIyaWQlMjIlM0ElMjI5VnFubDIzVzVHJTIyJTJDJTIycGFyYUlkeCUyMiUzQTAlMkMlMjJzcmMlMjIlM0ElMjJzZXF1bmNlJTIyJTJDJTIyZHN0JTIyJTNBJTIyJUU1JUJBJThGJUU1JTg4JTk3JTIyJTJDJTIybWV0YWRhdGElMjIlM0ElMjIlMjIlMkMlMjJtZXRhRGF0YSUyMiUzQSU1QiU1RCUyQyUyMnRleHQlMjIlM0ElMjJzZXF1bmNlJTIyJTdEJTVEJTdEJTVE"&gt;Do you need to choose use PMIC IC or not?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 23 Oct 2024 07:16:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1979939#M230027</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2024-10-23T07:16:34Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1979947#M230028</link>
      <description>&lt;P&gt;Yes, I want to choose PMIC, so please recommend and can you please explain to me a power on/off sequence?&lt;/P&gt;</description>
      <pubDate>Wed, 23 Oct 2024 07:24:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1979947#M230028</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-23T07:24:01Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980045#M230031</link>
      <description>&lt;P&gt;Yes, I want to choose to use PMIC, Please suggest.&lt;/P&gt;</description>
      <pubDate>Wed, 23 Oct 2024 09:09:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980045#M230031</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-23T09:09:27Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980072#M230033</link>
      <description>Please share reference design file and suggest PMIC IC</description>
      <pubDate>Wed, 23 Oct 2024 09:39:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980072#M230033</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-23T09:39:01Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980690#M230077</link>
      <description>&lt;P&gt;Details you can see in our datasheet:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Rita_Wang_0-1729738996362.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/306579i83F955862BBFB583/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Rita_Wang_0-1729738996362.png" alt="Rita_Wang_0-1729738996362.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;For the design with PMIC, I email to you.&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 03:03:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980690#M230077</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2024-10-24T03:03:48Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980716#M230078</link>
      <description>&lt;P&gt;Thank You so much for your response.&lt;BR /&gt;I am using&amp;nbsp;&lt;SPAN&gt;DDR3L SDRAM so, any special power supply required to manage DDR3L in the NXP datasheet mentioned is 1.35V.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 03:25:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980716#M230078</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-24T03:25:51Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980758#M230081</link>
      <description>&lt;P&gt;Can you please verify the PMIC Parts number?&lt;BR /&gt;MC32PF1550A0EP&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 04:18:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980758#M230081</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-24T04:18:48Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980821#M230086</link>
      <description>&lt;P&gt;Yes, for DDR3L the power is 1.35, You can use the DDR3L on the i.MX6ULL just following the Hardware Development Guide for the i.MX 6ULL Applications Processor.&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 05:34:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980821#M230086</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2024-10-24T05:34:38Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980826#M230087</link>
      <description>&lt;P&gt;Yes, it is&amp;nbsp;&lt;A href="https://www.nxp.com/products/power-management/pmics-and-sbcs/pmics/pmic-with-1a-li-plus-linear-battery-charger-for-low-power-processor-systems:PF1550" target="_blank"&gt;PMIC with 1A Li+ Linear Battery Charger | NXP Semiconductors&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 05:37:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980826#M230087</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2024-10-24T05:37:52Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980833#M230088</link>
      <description>&lt;P&gt;Thank You so much for your support!&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 05:41:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980833#M230088</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-24T05:41:01Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980881#M230089</link>
      <description>&lt;P&gt;I am using DDR3L and am a little bit confused about the VDD_SOC_IN voltage configuration. According to a datasheet, its range is from 1.15V to 1.3V. So,&lt;SPAN&gt;&amp;nbsp;which voltage is suitable for my application?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 06:18:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980881#M230089</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-24T06:18:21Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980996#M230093</link>
      <description>&lt;P&gt;PMIC can out put what the voltage you want for the&amp;nbsp;VDD_ARM_SOC_IN, so you do not care about it, if you choose the PMIC in your design.&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 07:55:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1980996#M230093</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2024-10-24T07:55:04Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1981005#M230095</link>
      <description>&lt;P&gt;But, I don't know exactly which voltage is chosen for&amp;nbsp;&lt;SPAN&gt;VDD_SOC_IN.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Does it affect DDR3L if I choose 1.05V or 1.225V?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 08:03:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1981005#M230095</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-24T08:03:02Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1983600#M230226</link>
      <description>&lt;P&gt;For the&amp;nbsp;VDD_SOC_IN it need 1.275 to 1.5 for 528MHz for A7 core work, and&amp;nbsp; 1.375 to 1.5 for 900MHz for A7 core work.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Rita_Wang_0-1730181519830.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/307401i083B2E1103D5D4E3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Rita_Wang_0-1730181519830.png" alt="Rita_Wang_0-1730181519830.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;From the design I share to you, you can see that for the&amp;nbsp;VDD_SOC_IN it is supply from the SW1 of the PF1550.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Rita_Wang_0-1730189285660.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/307417i207CC1641C7DD0B9/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Rita_Wang_0-1730189285660.png" alt="Rita_Wang_0-1730189285660.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Rita_Wang_1-1730189349782.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/307418iD6FB4C88D247B585/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Rita_Wang_1-1730189349782.png" alt="Rita_Wang_1-1730189349782.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;From the PF1550 datasheet you can see that the SW1 can supply:&lt;/P&gt;
&lt;P&gt;SW1, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps&lt;/P&gt;
&lt;P&gt;So it can supply what the&amp;nbsp;VDD_SOC_IN need, so you do not know what the exactly the value it is.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/products/power-management/pmics-and-sbcs/pmics/pmic-with-1a-li-plus-linear-battery-charger-for-low-power-processor-systems:PF1550" target="_blank"&gt;PMIC with 1A Li+ Linear Battery Charger | NXP Semiconductors&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/data-sheet/PF1550.pdf" target="_blank"&gt;PF1550, Power management integrated circuit (PMIC) for low power application - Data sheet&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Rita_Wang_2-1730189440591.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/307419iC18EC97766064AC2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Rita_Wang_2-1730189440591.png" alt="Rita_Wang_2-1730189440591.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;For the DDR3L, the Voltage is 1.35V, and the power for the DDR is from NVCC_DRAM power, DDR will effect by it:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Rita_Wang_0-1730168312112.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/307350i04D7FEEA9BB09BCB/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Rita_Wang_0-1730168312112.png" alt="Rita_Wang_0-1730168312112.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 29 Oct 2024 08:12:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1983600#M230226</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2024-10-29T08:12:35Z</dc:date>
    </item>
    <item>
      <title>Re: Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1983631#M230230</link>
      <description>&lt;P&gt;Thank You so much for your support.&lt;/P&gt;</description>
      <pubDate>Tue, 29 Oct 2024 08:44:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Designing-a-schematic-for-NXP-imx6ull-MCIMX6Y2DVM09AB/m-p/1983631#M230230</guid>
      <dc:creator>Nikunj_Solanki</dc:creator>
      <dc:date>2024-10-29T08:44:59Z</dc:date>
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