Cortex-M4(i.MX8M-MINI): To what extent are the ITCM and DTCM areas affected by the MPU settings?

Takashi_Kashiwagi — Sun, 13 Oct 2024 02:29:08 GMT

Hi Community

I have a question about the i.MX8M-MINI Cortex-M4 MPU.

I have set up the MPU as shown below, but for the ITCM (0x1FFE0000-0x1FFFFFFF) and DTCM(0x20000000 - 0x2001FFFF) areas, will the TypeExtField /IsShareable /IsCacheable /IsBufferable items be applied as set?

Or will some of them be ignored?

```
/* Region 1 TCML[0x1FFE0000 - 0x1FFFFFF]: Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(1u, 0x1FFE0000U);
MPU->RASR = ARM_MPU_RASR(0u, ARM_MPU_AP_FULL, 1u, 0u, 0u, 0u, 0u, ARM_MPU_REGION_SIZE_128KB);
/* Region 2 TCMU[0x20000000U - 0x20020000U]: Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(2u, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(1u, ARM_MPU_AP_FULL, 1u, 0u, 0u, 0u, 0u, ARM_MPU_REGION_SIZE_128KB);
```

Best Regards,
KASHIWAGI Takashi

topic Cortex-M4(i.MX8M-MINI): To what extent are the ITCM and DTCM areas affected by the MPU settings? in i.MX Processors

Cortex-M4(i.MX8M-MINI): To what extent are the ITCM and DTCM areas affected by the MPU settings?