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    <title>i.MX ProcessorsのトピックEDAC Driver for IMX8DXL</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/EDAC-Driver-for-IMX8DXL/m-p/1965359#M229183</link>
    <description>&lt;P&gt;Is there a Linux EDAC driver that can be used with the IMX8DXL?&amp;nbsp; The reference manual lists out the ECC registers for the IMX8DXL, but are the DDRC registers available on the A35 cores?&lt;/P&gt;&lt;P&gt;The reference manual just says the DDRC Base address is 0h.&amp;nbsp; Is this correct?&lt;/P&gt;&lt;P&gt;I'm trying to use the Synopsys EDAC driver.&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Will this driver work with the IMX8DXL DDRC?&lt;/LI&gt;&lt;LI&gt;If it will work, what value should I put in the reg entry in the device tree to get this to work?&lt;/LI&gt;&lt;/UL&gt;</description>
    <pubDate>Tue, 01 Oct 2024 19:19:23 GMT</pubDate>
    <dc:creator>chanks</dc:creator>
    <dc:date>2024-10-01T19:19:23Z</dc:date>
    <item>
      <title>EDAC Driver for IMX8DXL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EDAC-Driver-for-IMX8DXL/m-p/1965359#M229183</link>
      <description>&lt;P&gt;Is there a Linux EDAC driver that can be used with the IMX8DXL?&amp;nbsp; The reference manual lists out the ECC registers for the IMX8DXL, but are the DDRC registers available on the A35 cores?&lt;/P&gt;&lt;P&gt;The reference manual just says the DDRC Base address is 0h.&amp;nbsp; Is this correct?&lt;/P&gt;&lt;P&gt;I'm trying to use the Synopsys EDAC driver.&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Will this driver work with the IMX8DXL DDRC?&lt;/LI&gt;&lt;LI&gt;If it will work, what value should I put in the reg entry in the device tree to get this to work?&lt;/LI&gt;&lt;/UL&gt;</description>
      <pubDate>Tue, 01 Oct 2024 19:19:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EDAC-Driver-for-IMX8DXL/m-p/1965359#M229183</guid>
      <dc:creator>chanks</dc:creator>
      <dc:date>2024-10-01T19:19:23Z</dc:date>
    </item>
    <item>
      <title>Re: EDAC Driver for IMX8DXL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EDAC-Driver-for-IMX8DXL/m-p/1965403#M229189</link>
      <description>&lt;P&gt;I saw in the reference manual that there is a DRC0 in the Db Memory Map, but also it says that the Db Memory map is accessible only by the SCU. Is this the DDR Controller?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I tried the following in my device tree, but this produces a kernel panic:&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;&amp;amp;ddr_subsys {
        edacmc: memory-controller@5c000000 {
                compatible = "snps,ddrc-3.80a";
                reg = &amp;lt;0x5c000000 0x10000&amp;gt;;
                interrupts = &amp;lt;GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH&amp;gt;, /* Correctable error */
                             &amp;lt;GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH&amp;gt;, /* Uncorrectable error */
                             &amp;lt;GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH&amp;gt;; /* Address Channel Error */
               interrupt-names = "ecc_ce", "ecc_ue", "ecc_ap";
        };
};&lt;/LI-CODE&gt;</description>
      <pubDate>Tue, 01 Oct 2024 21:28:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EDAC-Driver-for-IMX8DXL/m-p/1965403#M229189</guid>
      <dc:creator>chanks</dc:creator>
      <dc:date>2024-10-01T21:28:21Z</dc:date>
    </item>
    <item>
      <title>Re: EDAC Driver for IMX8DXL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EDAC-Driver-for-IMX8DXL/m-p/1965874#M229220</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Unfortunately, there is not a specific EDAC linux driver for i.mx8dxl.&lt;/P&gt;
&lt;P&gt;You can refer to the&amp;nbsp;&lt;A href="https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi" target="_self"&gt;imx8-ss-ddr.dtsi&lt;/A&gt;, there is defined the ddr_subsys node for i.MX8.&lt;/P&gt;
&lt;P&gt;Also the&amp;nbsp;&lt;A href="https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi#L20" target="_self"&gt;imx8dxl-ss-ddr.dtsi&lt;/A&gt;.&lt;/P&gt;
&lt;P&gt;Those dtsi are defined on the&amp;nbsp;&lt;A href="https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8dxl.dtsi#L281C11-L281C30" target="_self"&gt;imx8dxl.dtsi&lt;/A&gt;.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Salas.&lt;/P&gt;</description>
      <pubDate>Wed, 02 Oct 2024 17:57:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EDAC-Driver-for-IMX8DXL/m-p/1965874#M229220</guid>
      <dc:creator>Manuel_Salas</dc:creator>
      <dc:date>2024-10-02T17:57:40Z</dc:date>
    </item>
    <item>
      <title>Re: EDAC Driver for IMX8DXL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EDAC-Driver-for-IMX8DXL/m-p/1965877#M229222</link>
      <description>I've checked out those dtsi files before but it's not really helpful for the issue. Is the DDRC accessible from the A cores? If so, what is the memory address? I think I can adapt the existing EDAC driver to work if I only knew the correct address.</description>
      <pubDate>Wed, 02 Oct 2024 18:07:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EDAC-Driver-for-IMX8DXL/m-p/1965877#M229222</guid>
      <dc:creator>chanks</dc:creator>
      <dc:date>2024-10-02T18:07:47Z</dc:date>
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