i.MX Processorsのトピックi.MX93 lcdif clock rate calculation app note

i.MX93 lcdif clock rate calculation app note

tim_cargt — Mon, 23 Sep 2024 21:32:01 GMT

I am upgrading an existing i.MX93 design from Mickledore to Scarthgap and have run into an issue with display timing.

My board uses mipi-dsi display and works fine with Mickledore. When I upgrade to Scarthgap, the display timing is off. All clock tree timings look identical (according to /sys/kernel/debug/clk/clk_summary). I can modify the pixel clock inside of the driver (panel-ilitek-ili9881c) and that has an impact, but I'm unable to find a clock rate that makes the display operate properly. (Also, this seems wrong to me since it was working fine in Mickledore.)

I can also modify the lcdif clock rates in the device tree. Again, this has an impact, but I'm unable to find a combination that makes my display work properly.

&lcdif { status = "okay"; assigned-clock-rates = <445333333>, <148444444>, <400000000>, <133333333>; };

Is there an app note that explains how to calculate the proper clock rates for lcdif?

Thanks,

Tim

Re: i.MX93 lcdif clock rate calculation app note

joanxie — Wed, 25 Sep 2024 01:33:47 GMT

what detailed lcdif clock do you need for your display?

Re: i.MX93 lcdif clock rate calculation app note

tim_cargt — Wed, 25 Sep 2024 02:24:46 GMT

We will eventually need to support multiple displays, but I only need the timing I posted in the original message. I am able to use that timing with a 50 MHz pixel clock with Mickledore. I cannot do the same with Scarthgap. Something is fundamentally different even though all of the clock tree values are identical between builds.

I would like to understand what changed between Mickledore and Scarthgap with regards to lcdif timing.

Re: i.MX93 lcdif clock rate calculation app note

joanxie — Wed, 25 Sep 2024 07:38:06 GMT

could you share your lcdif settings in the dts file with Mickledore? for pll, I checked the different between with Mickledore and Scarthgap is the pll table, I don't know if this would affect your display or not since this is depends on your settings in the dts, maybe you can check it by yourself, the fracn_tbl

https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/drivers/clk/imx/clk-fracn-gppll.c

Re: i.MX93 lcdif clock rate calculation app note

tim_cargt — Thu, 26 Sep 2024 17:08:05 GMT

The imx_fracn_gppll_rate_table rate table is:

static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(1700000000U, 141, 0, 0, 1, 2), PLL_FRACN_GP(1400000000U, 175, 0, 0, 1, 3), PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4), PLL_FRACN_GP(900000000U, 150, 0, 0, 1, 4), PLL_FRACN_GP(800000000U, 200, 0, 0, 1, 6), PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10), PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12) };

My device tree has the following:

&lcdif { status = "okay"; assigned-clock-rates = <445333333>, <148444444>, <400000000>, <133333333>; };

and is based on the node in imx93.dtsi:

lcdif: lcd-controller@4ae30000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx93-lcdif"; reg = <0x4ae30000 0x10000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; fsl,gpr = <&media_blk_ctrl>; clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>, <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_LCDIF_GATE>; clock-names = "pix", "disp-axi", "disp-apb"; assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>, <&clk IMX93_CLK_MEDIA_DISP_PIX>, <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>; assigned-clock-parents = <&clk IMX93_CLK_24M>, <&clk IMX93_CLK_VIDEO_PLL>, <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>; status = "disabled"; lcdif_disp: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; lcdif_to_dsi: endpoint@0 { reg = <0>; remote-endpoint = <&dsi_to_lcdif>; }; lcdif_to_ldb: endpoint@1 { reg = <1>; remote-endpoint = <&ldb_ch0>; }; lcdif_to_dpi: endpoint@2 { reg = <2>; remote-endpoint = <&dpi_to_lcdif>; }; }; };

Can you please explain

1. How should I calculate the assigned-clock-rates in the device tree?

2. How do those assigned-clock-rates relate to the imx_fracn_gppll_rate_table?

3. What is the meaning behind the values in the imx_fracn_gppll_rate_table?

4. How can I add/modify rows in the imx_fracn_gppll_rate_table?

Re: i.MX93 lcdif clock rate calculation app note

joanxie — Fri, 27 Sep 2024 06:37:10 GMT

1. How should I calculate the assigned-clock-rates in the device tree?

> the clock in the dts is depends on your display spec

2. How do those assigned-clock-rates relate to the imx_fracn_gppll_rate_table?

>refer to the dtsi file as below

assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>,
<&clk IMX93_CLK_MEDIA_DISP_PIX>,
<&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_MEDIA_APB>;

the pll clock is got from the fracn_tbl

3. What is the meaning behind the values in the imx_fracn_gppll_rate_table?

>you can find the definition in the driver as below

#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \
{ \
.rate = (_rate), \
.mfi = (_mfi), \
.mfn = (_mfn), \
.mfd = (_mfd), \
.rdiv = (_rdiv), \
.odiv = (_odiv), \
}

The root source clock for VIDEO_PLL is
Fvco = Fref * (mfi + mfn / mfd), Fref = 24M,

rate = Fvco / (rdiv + odiv )

for example, you need add 445333333 like

PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),

then Fvco= 24x (167+0/1)=4008, rate=4008/9=445.333333

4. How can I add/modify rows in the imx_fracn_gppll_rate_table?

> use the formula I posted in the question 3, to set mfi, mfn, mfd, rdiv and odiv, calculate the pll clock you need, then put it in the table , hope my description is clear for you

Re: i.MX93 lcdif clock rate calculation app note

tim_cargt — Tue, 01 Oct 2024 14:23:14 GMT

Thank you for your response. It is starting to make sense to me now. I do have a few more questions.

1. Does IMX93_CLK_MEDIA_DISP_PIX represent my pixel clock? If so, I would like to use an example of a 65 MHz pixel clock, so I set this to 65000000. Then I think I need to find a value for IMX93_CLK_VIDEO_PLL that is a multiple of that frequency. Is that correct?

2. Are there any rules about what kind of multiple it needs to be? Previously it seemed to always be 7x, but for the i.MX93, I have seen examples where it is 3x.

One of the existing values in the imx_fracn_gppll_rate_table is 10x. I tried to use that, by setting my clock rates in the device tree to the following:

assigned-clock-rates = <650000000>, <65000000>, <400000000>, <133333333>;

Do I understand it correctly so far?

3. How do I determine the values for IMX93_CLK_MEDIA_AXI and IMX93_CLK_MEDIA_APB? Do those depend on the values for the other two clock frequencies?

Thanks again,

Tim

Re: i.MX93 lcdif clock rate calculation app note

SoftTransistor — Fri, 04 Oct 2024 14:06:06 GMT

2. Are there any rules about what kind of multiple it needs to be? Previously it seemed to always be 7x, but for the i.MX93, I have seen examples where it is 3x.

It needs to be 7x. This is because the lvds data lines frequencies are 7 times higher than the clock. see https://www.kernel.org/doc/Documentation/devicetree/bindings/display/lvds-data-mapping.yaml

Re: i.MX93 lcdif clock rate calculation app note

tim_cargt — Fri, 04 Oct 2024 14:37:47 GMT

I'm not sure this is still the case. See this example from NXP that shows a 3x multiplier.

https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts#L427

Re: i.MX93 lcdif clock rate calculation app note

SoftTransistor — Mon, 07 Oct 2024 09:44:22 GMT

I'm no expert at reading DT files, but I don't see any nodes related to lvds (no ldb, lvds panel). I see some dsi though, might related to that.

Re: i.MX93 lcdif clock rate calculation app note

tim_cargt — Mon, 07 Oct 2024 12:46:24 GMT

This design uses a mipi display. I have added a new panel to the ili9881c driver. Again, this was working in Mickeldore, but not in Scarthgap.

&dsi { #address-cells = <1>; #size-cells = <0>; status = "okay"; panel@0 { compatible = "custom,g156400", "ilitek,ili9881c"; reg = <0>; pinctrl-names = "default"; rotation = <90>; pinctrl-0 = <&pinctrl_lcd>; reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; backlight = <&pwm_backlight>; status = "okay"; port { panel_in: endpoint { remote-endpoint = <&dsi_out>; }; }; }; ports { port@1 { reg = <1>; dsi_out: endpoint { remote-endpoint = <&panel_in>; }; }; }; };

My original problem turned out to be a mistake in the driver addition where I claimed support for MIPI_DSI_MODE_VIDEO_BURST mode set when it should not. The following changes were then included when I upgraded from Mickledore to Scarthgap causing a timing issue:
https://github.com/nxp-imx/linux-imx/commit/08af66e502f37716894ab8f8180de4bc71a972f7

So I have resolved my original issue, but I would still like to better understand how to determine clock rates to add support for new panel timing.