i.MX Processors中的主题 Re: Interfacing SRAM with imxrt1062

Interfacing SRAM with imxrt1062

VishalAvg — Mon, 02 Sep 2024 09:22:25 GMT

Hello everyone, I need assistance in reviewing my design. This is my first time designing with the IMXRT1062 processor.

The primary goal of my design is to interface the IMXRT1062 with external SRAM using ADMUX mode and external flash using QSPI.

I have completed the circuit design and would like to know if any changes or additions are required for the circuit to function flawlessly.

I am utilizing Latches 74HC574 to separate the address and data buses, a buffer to control read and write operations, and a decoder IC to increase chip select options for SRAM applications.

Please comments and give your valuable advice.

Re: Interfacing SRAM with imxrt1062

Omar_Anguiano — Wed, 04 Sep 2024 00:05:57 GMT

Your design looks well. It followed table 25-6 to interface the SRAM pins to RT1060.
The capacitor on DQS pins might not be needed however this is evaluated by testing, the value is chosen by testing different capacitor values.

Best regards,
Omar

Re: Interfacing SRAM with imxrt1062

VishalAvg — Wed, 04 Sep 2024 06:21:51 GMT

Thank you sir for your valuable advice and suggestion.

Re: Interfacing SRAM with imxrt1062

VishalAvg — Mon, 09 Sep 2024 05:54:21 GMT

Hello,

I have one more question, what is the use of configurable clock 0 and clock 1 (SEMC_CLKX0 and SEMC_CLKX1 ) ?

Is there any use of this clock signals to interface SRAM? I am using CY62126EV30LL-45ZSXI SRAM.

I attached datasheet also.

Re: Interfacing SRAM with imxrt1062

VishalAvg — Tue, 10 Sep 2024 07:37:41 GMT

Please Reply this post....

Re: Interfacing SRAM with imxrt1062

Omar_Anguiano — Tue, 10 Sep 2024 18:13:14 GMT

These clocks are used on SYNC mode of NOR/SRAM devices. For your specific memory, there is no use of the clock signals as there is no pad for them.

Best regards,
Omar