<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX Processors中的主题 Re: Why the PIXCLK frequency is not consistant ?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Why-the-PIXCLK-frequency-is-not-consistant/m-p/146490#M228</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Florent Auger,&lt;/P&gt;&lt;P&gt;You supply me a great answer. Thanks a lot.&lt;/P&gt;&lt;P&gt;I will adjust the pixclk frequency for a better duty cycle.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 22 Mar 2012 07:19:25 GMT</pubDate>
    <dc:creator>leejey</dc:creator>
    <dc:date>2012-03-22T07:19:25Z</dc:date>
    <item>
      <title>Why the PIXCLK frequency is not consistant ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Why-the-PIXCLK-frequency-is-not-consistant/m-p/146488#M226</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am using iMX51 connected a WVGA LCD.&lt;/P&gt;&lt;P&gt;I&amp;nbsp;measured the PIXCLK frequency and it is a variant waveform. It means that the high time on the clock pulse varies in a scope. As&amp;nbsp;we know that Pixel clock frequency is directly related with the frame refresh rate. But I don't know why?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 21 Mar 2012 10:43:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Why-the-PIXCLK-frequency-is-not-consistant/m-p/146488#M226</guid>
      <dc:creator>leejey</dc:creator>
      <dc:date>2012-03-21T10:43:08Z</dc:date>
    </item>
    <item>
      <title>Re: Why the PIXCLK frequency is not consistant ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Why-the-PIXCLK-frequency-is-not-consistant/m-p/146489#M227</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;The typical structure for the IPU driver of Linux is the following.&lt;/P&gt;&lt;P&gt;struct fb_videomode {&lt;BR /&gt; const char *name;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* optional */&lt;BR /&gt;u32 refresh;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* this parameter is ignored */&lt;BR /&gt;u32 xres;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* pixel */&lt;BR /&gt;u32 yres;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* pixel */&lt;BR /&gt;u32 pixclock;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* pico second */&lt;BR /&gt;u32 left_margin;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* pix_clk */&lt;BR /&gt;u32 right_margin;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* pix_clk */&lt;BR /&gt;u32 upper_margin;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* line */&lt;BR /&gt;u32 lower_margin;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* line */&lt;BR /&gt;u32 hsync_len;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* pix_clk */&lt;BR /&gt;u32 vsync_len;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/* line */&lt;BR /&gt;u32 sync;&lt;BR /&gt;u32 vmode;&lt;BR /&gt;u32 flag;&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The timing diagrams are the following:&lt;BR /&gt; &lt;BR /&gt;___ &amp;lt;- hsync_len -&amp;gt;______________________________________&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp; |____________|&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;lt;--- xres ---&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |________&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;- left_margin -&amp;gt; _________ &amp;lt;- right_margin -&amp;gt;&lt;BR /&gt;______________________________|&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; |_______________________&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;___ &amp;lt;- vsync_len -&amp;gt; ____________________________________________&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; |_____________|&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;-------- yres ------&amp;gt; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; |____&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;lt;- upper_margin -&amp;gt;___&amp;nbsp;&amp;nbsp; _..._ &amp;nbsp;&amp;nbsp; ___ &amp;lt;- lower_margin -&amp;gt;&lt;BR /&gt;________________________________| &amp;nbsp; &amp;nbsp; |_|&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;nbsp; |_| &amp;nbsp; &amp;nbsp; |____________________&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The period of the pixel clock is given in pico seconds. The dividers inside the IPU are not integer, and depending on the value of pixclock, the clock might have a duty cycle that is different from 50%.&lt;/P&gt;&lt;P&gt;The calculation for the dividers being made automatically by the driver, it is sometimes necessary to slightly adjust pixclock to a higher or lower value to get a nice clock.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 21 Mar 2012 15:59:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Why-the-PIXCLK-frequency-is-not-consistant/m-p/146489#M227</guid>
      <dc:creator>FlorentAuger</dc:creator>
      <dc:date>2012-03-21T15:59:17Z</dc:date>
    </item>
    <item>
      <title>Re: Why the PIXCLK frequency is not consistant ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Why-the-PIXCLK-frequency-is-not-consistant/m-p/146490#M228</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Florent Auger,&lt;/P&gt;&lt;P&gt;You supply me a great answer. Thanks a lot.&lt;/P&gt;&lt;P&gt;I will adjust the pixclk frequency for a better duty cycle.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 22 Mar 2012 07:19:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Why-the-PIXCLK-frequency-is-not-consistant/m-p/146490#M228</guid>
      <dc:creator>leejey</dc:creator>
      <dc:date>2012-03-22T07:19:25Z</dc:date>
    </item>
  </channel>
</rss>

