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    <title>topic Re: Endpoint Interrupt via PCIe in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250596#M22783</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;BR /&gt;As I know that, there is no such kind of INT.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regard&lt;/P&gt;&lt;P&gt;Richard&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 06 Dec 2013 02:09:12 GMT</pubDate>
    <dc:creator>richard_zhu</dc:creator>
    <dc:date>2013-12-06T02:09:12Z</dc:date>
    <item>
      <title>Endpoint Interrupt via PCIe</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250595#M22782</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Is there a way to interrupt the i.MX6 via PCIe when it is operating in endpoint (EP) mode? When the device is setup in root complex (RC) mode there are a variety of spec-based PCIe interrupt sources, however, I can't seem to find a method to interrupt the processor over the PCIe bus when it is operating in EP mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There are the software interrupts available in the ARM MPCore, however, these are located on a bus internal to the ARM core. Therefore, I won't be able to access them from the RC device. Is there another set of software interrupts available when the i.MX6 is in EP mode that I can trigger from the RC device?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Sep 2013 19:51:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250595#M22782</guid>
      <dc:creator>scottkanowitz</dc:creator>
      <dc:date>2013-09-25T19:51:14Z</dc:date>
    </item>
    <item>
      <title>Re: Endpoint Interrupt via PCIe</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250596#M22783</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;BR /&gt;As I know that, there is no such kind of INT.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regard&lt;/P&gt;&lt;P&gt;Richard&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Dec 2013 02:09:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250596#M22783</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2013-12-06T02:09:12Z</dc:date>
    </item>
    <item>
      <title>Re: Endpoint Interrupt via PCIe</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250597#M22784</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;the correct answer is: There is no standardized (as PCI standard) way of interrupting the EP. However there are a few ways how to do that in a proprietary way.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt; Matevz&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Apr 2014 10:56:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250597#M22784</guid>
      <dc:creator>matevzlangus</dc:creator>
      <dc:date>2014-04-02T10:56:36Z</dc:date>
    </item>
    <item>
      <title>Re: Endpoint Interrupt via PCIe</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250598#M22785</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can you give an example? We're looking for a way to do that.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards&lt;/P&gt;&lt;P&gt;Andreas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 18 Aug 2014 19:16:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250598#M22785</guid>
      <dc:creator>andreaskarlsson</dc:creator>
      <dc:date>2014-08-18T19:16:20Z</dc:date>
    </item>
    <item>
      <title>Re: Endpoint Interrupt via PCIe</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250599#M22786</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Could you give examples?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 03 Jan 2018 22:09:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250599#M22786</guid>
      <dc:creator>brettstahlman</dc:creator>
      <dc:date>2018-01-03T22:09:20Z</dc:date>
    </item>
    <item>
      <title>Re: Endpoint Interrupt via PCIe</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250600#M22787</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;configure some other peripheral in i.MX6 EP device (not PCIe) for example GPIO in such a way that writing a specific value to a register belonging to that peripheral (GPIO) will cause GPIO interrupt to fire and interrupt local CPU.&lt;/P&gt;&lt;P&gt;Then create inbound mapping on i.MX6 EP device so that PCIe cycles from PCIe bus will be routed correctly and will hit before mentioned register.&lt;/P&gt;&lt;P&gt;From external device write the value over PCIe to the correct address and it will end like write transaction to the register inside GPIO which will fire an interrupt.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;&amp;nbsp; Matevz&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 Jan 2018 21:58:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250600#M22787</guid>
      <dc:creator>matevzlangus</dc:creator>
      <dc:date>2018-01-18T21:58:52Z</dc:date>
    </item>
    <item>
      <title>Re: Endpoint Interrupt via PCIe</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250601#M22788</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Understood. Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 Jan 2018 23:45:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250601#M22788</guid>
      <dc:creator>brettstahlman</dc:creator>
      <dc:date>2018-01-18T23:45:33Z</dc:date>
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