What addresses are the IMX7D integrated power switch registers mapped to?

takayuki_ishii — Thu, 08 Aug 2024 10:20:37 GMT

Hello community,

Our product is a battery-powered portable device.

We do not use Linux BSP but ROTS for this product.

In this product, some i.MX7D devices have a very large VDD_SOC leakage current

during power saving, resulting in a very short standby time.

So we plan to control SW_SOC_PD switch.

In following community thread, it say that

please refer to section 5.5.11 (GPC PGC Memory Map/Register Definition) of i.MX 7Dual Applications Processor Reference Manual, Rev. 0.1, 08/2016

How to control the i.MX7D integrated power switches ON/OFF

However, while the six switches and corresponding registers can be guessed, SW_SOC_PD and SW_FUSE are not clear.

Q1. Is the ON/OFF bit of SW_SOC_PD correct with the PCR bit (bit 0) of the GPC PGC Control Register (GPC_PGC_MIX_CTRL)?

We are currently reviewing the power saving implementation by comparing it with the Linux BSP source code.

In Linux source code "/drivers/soc/imx/gpcv2.c", it say that

/* * The PGC offset values in Reference Manual * (Rev. 1, 01/2018 and the older ones) GPC chapter's * GPC_PGC memory map are incorrect, below offset * values are from design RTL. */ #define IMX7_PGC_MIPI 16 #define IMX7_PGC_PCIE 17 #define IMX7_PGC_USB_HSIC 20 #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)

And optee-os source "/core/drivers/pm/imx/suspend/psci-suspend-imx7.S"

#define MX7_SRC_GPR1 0x74 #define MX7_SRC_GPR2 0x78 #define GPC_PGC_C0 0x800 #define GPC_PGC_FM 0xa00

So it have difference between reference manual and Linux BSP source code.

PGC module name	Reference Manual	Linux BSP code
PGC for A7 core0	0x303A_0800	0x303A_0800
PGC for A7 core1	0x303A_0840
PGC for A7 SCU	0x303A_0880
PGC for fastmix/megamix	0x303A_0890(GPC_PGC_SCU_AUXSW?) 0x303A_08C0(GPC_PGC_MIX_CTRL?)	0x303A_0A00(GPC_PGC_FM)
PGC for MIPI PHY	0x303A_0900	0x303A_0C00 BASE + (0x800 + (16) * 0x40)
PGC for PCIE_PHY	0x303A_940	0x303A_0C40 BASE + (0x800 + (17) * 0x40)
PGC for USB HSIC PHY	0x303A_0D00	0x303A_0D00 BASE + (0x800 + (20) * 0x40)

Q2. Which is correct address?

Best regards,

Ishii.

Re: What addresses are the IMX7D integrated power switch registers mapped to?

Chavira — Thu, 08 Aug 2024 16:11:45 GMT

Hi @takayuki_ishii!

Thank you for contacting NXP Support!

You have to refer to the Reference Manual.

Best Regards!

Chavira

Re: What addresses are the IMX7D integrated power switch registers mapped to?

takayuki_ishii — Thu, 15 Aug 2024 09:32:42 GMT

Hello @Chavira

Thank you for your answered.

> You have to refer to the Reference Manual.

I will write the source code by referring to the reference manual.

> Q1. Is the ON/OFF bit of SW_SOC_PD correct with the PCR bit (bit 0) of the GPC PGC Control Register (GPC_PGC_MIX_CTRL)?

What do you think of the answer to Q1?

I would appreciate your cooperation.

Best regards,

Ishii.

Re: What addresses are the IMX7D integrated power switch registers mapped to?

Chavira — Thu, 15 Aug 2024 17:49:13 GMT

Hi @takayuki_ishii!

The GPC_PGC_MIX_CTRL should be PGC for fastmix/megamix and according to the diagram below.

Best Regards!

Chavira

topic Re: What addresses are the IMX7D integrated power switch registers mapped to? in i.MX Processors

What addresses are the IMX7D integrated power switch registers mapped to?

Re: What addresses are the IMX7D integrated power switch registers mapped to?

Re: What addresses are the IMX7D integrated power switch registers mapped to?

Re: What addresses are the IMX7D integrated power switch registers mapped to?