topic Re: i.mx 93 TPM timer configuration in i.MX Processors

i.mx 93 TPM timer configuration

Karr — Thu, 11 Jul 2024 19:49:29 GMT

I'm working with a SoM based on the i.mx 9352. I'm looking for a way on how to create a chain of TPM timers in the firmware for the Cortex-M core. In my case, I use TPM6_EXTCLK pin for receiving external clock source from a crystal and then it is used for generating signals on TMP6_CH1, TMP6_CH2 and TMP6_CH3. I want to use TMP6_CH0 as an external source for the TMP5. Is it possible to use an output of the TMP6_CH0 as a an external clock source for TMP5_EXTCLK? Or is this only possible by physically connecting the TMP6_CH0 and TMP5_EXTCLK pins?

Maybe it is possible by using an external trigger source? It is mentioned in the RM for i.mx 93 that I should see the chip-specific TPM information for available external trigger options, but I don't know where to find this information - is it an extra document about i.mx 9352?

Re: i.mx 93 TPM timer configuration

Manuel_Salas — Thu, 11 Jul 2024 23:04:51 GMT

Hello @Karr

Look the below Block diagram:

In chapter 67.3.10.1 Counter Clock mode of reference manual is mentioned:

SC[CMOD] either disables the TPM counter or enables one of the three possible clock sources for the TPM counter. After any reset, SC[CMOD] becomes 0, which disables the TPM counter. You can configure SC[CMOD] for one of the following counter clock sources:

• Asynchronous counter clock
• External clock input pin
• External trigger source

You can read or write to SC[CMOD] at any time. Disabling the TPM counter by writing 0 to SC[CMOD] does not affect the TPM counter value or other registers, but the TPM counter clock domain must acknowledge this disabling action before SC[CMOD] becomes 0.
The external clock input and external trigger source pass through a synchronizer. The TPM counter clock clocks this synchronizer to ensure that counter transitions are properly aligned to counter clock transitions. Therefore, to meet Nyquist criteria, and also considering jitter, the frequency of the external clock source must be less than half of the counter clock frequency.

Also, look the TRGSEL and TRGSRC bits on CONF register (67.7.1.16 Configuration (CONF)).

I hope this information can helps to achieve your application.

Best regards,

--... ...--

Salas.

Re: i.mx 93 TPM timer configuration

Karr — Fri, 12 Jul 2024 13:07:04 GMT

Hello @Manuel_Salas,

Thank you for the diagram! I used it to understand how I can clock my TIM6 by an external source, and it is a kind of working now.

My current issue is that I don't know is it possible to clock TIM5 with an output channel of TIM6 (e.g. TIM6_CH0). To illustrate better what I'm trying to build I've made this picture based on your diagram:

I see that TPM clock can be sourced either by an external clock source (case for TIM6) or by an external trigger source. And I thought that the external trigger source for TIM5 can be an output of the TIM6_CH0. But for now I see only one way how to do that - physically connect TIM6_CH0 pin to the TIM5_EXTCLK pin. Is there are some internal connections inside the MCU, which I can use instead of the physical connection?

So basically I want to have TIM5 and TIM6 been synchronized, and use extra TIM5's channels for sending events based on the TIM6_CH0 output.

Re: i.mx 93 TPM timer configuration

Manuel_Salas — Fri, 12 Jul 2024 14:17:42 GMT

Hello @Karr

Thank you for the clarification, I double checked and according the reference manual, there is not a way to do a "trigger" from TPMn to other TPM, it appears it must be a physical connection as you described.

Best regards,

--... ...--

Salas.

Re: i.mx 93 TPM timer configuration

Karr — Fri, 12 Jul 2024 15:04:30 GMT

Dear @Manuel_Salas ,

Clearly, thank you, then we will think about the physical routing in this case.

But maybe you know where to find the information about the external trigger options for TPM? RM manual for i.mx 93 refers to the chip-specific TPM information, but I cannot find it anywhere:

I've tried to search around the document, but seems this information is not available in the RM.