topic Re: i.MX8QM LVDS Dual Channel Mode in i.MX Processors

i.MX8QM LVDS Dual Channel Mode

HWasti — Thu, 27 Jun 2024 21:43:07 GMT

I am Looking at i.MX8 Quad Max datasheet, Table 81, "LVDS Pins"

Footnote 1 states: In single channel operation the maximum clock speed is 160Mhz; in dual channel operation with single synchronized clock the maximum clock speed is 85Mhz.

Running under Linux, I can place the LVDS display in the mode where even Pixels are on Channel A and odd pixels are on Channel B and each Channel has its own clock that synchronizes the 4 data pairs for that channel.

My question:

How do I place the output in the "Dual Channel" mode described above where all 8 data pairs are synchronized to the same clock. And which clock is this? The Channel A clock or the Channel B clock?

Thanks for your help.

Regards,

Hamid

Re: i.MX8QM LVDS Dual Channel Mode

brian14 — Fri, 28 Jun 2024 19:39:16 GMT

Hi @HWasti,

Thank you for contacting NXP Support!

For you first question, about implementation of dual mode you can use the following link as a reference:
IMX8QM: LVDS mirror dual mode reference patch - NXP Community

Here is described the changes that you will need to do. (Note that these patches are provided as a reference only)

Regarding, clock signal it refers to the CLK that is connected to Pixel Mapper. Please have a look to the i.MX8QM Reference Manual section 15.4.2 LVDS Display Bridge (LDB).

Re: i.MX8QM LVDS Dual Channel Mode

HWasti — Sat, 29 Jun 2024 00:54:33 GMT

Hi @brian14,

Thank you for the response. Unfortunately, I do not think we are talking about the same thing.

We already have the system working as shown in the second diagram in the link you provided, what that page labels "iMX8QM LVDS (Split Mode)"

As you will note, that image shows two data paths "CH0 1 clock lane + 4 data lane" and "CH1 1 clock lane +4 data lanes" This is identical to what Table 81 from my original post calls "Single Channel" where each 4 data lanes are paired with their own clock lane.

What we need to do is to go from here to the mode described in the second line of Table 81 called "Dual channel" where all 8 data lanes are clocked by a single "synchronized" clock lane.

Thanks.

Re: i.MX8QM LVDS Dual Channel Mode

brian14 — Tue, 02 Jul 2024 17:44:03 GMT

Hi @HWasti,

Thank you for the clarification.

Based on my research, there is no examples for the mode that you are describing. You can find examples for i.MX8QM on the link that I sent in my last reply.