i.MX93 FlexSPI Linux driver optimisation

Niebel-TQ — Tue, 18 Jun 2024 11:33:54 GMT

Hello,

in datasheet MCR0[RXCLKSR] = 0x1 is documented to deal with clocks up to 166 MHz. In reference manual additionally MCR0[RXCLKSR] = 0x2 is documented but no clock limit given. On a system with no STROBE pin available we try to enhance READ/WRITE performance.

Please clarify documentation for MCR0[RXCLKSR] = 0x2 regarding usable SPI SCLK frequencies.

Are there further restrictions in using this mode?

Additionally: are there plans to implement spi-mem dirmap for flexspi driver?

@danny_john

Re: i.MX93 FlexSPI Linux driver optimisation

Manuel_Salas — Thu, 20 Jun 2024 22:24:32 GMT

Hello,

You can look in Reference Manual:

36.4.15.4 Input timing for sampling with SCK output looped back from SCK pad

This section describes the input timing when sampling with the SCK output looped back from the SCK pad (MCR0[RXCLKSRC] = 2). The input timing is similar to sampling with a dummy read strobe. SCK output toggles for all types of instructions, but internal dummy strobe only toggles for read and learn instructions. In this case, FlexSPI receives more data bits when sampling with SCK output. FlexSPI automatically ignores the redundant data bits sampled.

The only restriction is in SCKFREERUNEN

When SCLK Free-running is enabled, the data sampling loopback clock from SCLK pad is not supported.

There is not information available for spi-mem dirmap implementation.

I hope this can helps to you.

BR,

--... ...--

Salas.

i.MX ProcessorsのトピックRe: i.MX93 FlexSPI Linux driver optimisation

i.MX93 FlexSPI Linux driver optimisation

Re: i.MX93 FlexSPI Linux driver optimisation