i.MX ProcessorsのトピックRe: IPU/VPU cacheable memory access

IPU/VPU cacheable memory access

ofer_livny — Sun, 11 Aug 2013 18:32:56 GMT

I'm using iMX6Q, with freescale's linux 3.0.35, and my application is using the IPU and VPU intensively.

I have few processes which process the output of the IPU at the same time.

I noticed that my code runs a lot faster when the input is an image which is stored in regular memory (i.e. loaded from file), and slower when the image is in the IPU buffer (dma memory).

My guess is that the IPU buffers are not cached in the cpu's caches, which makes the memory access a lot slower.

While looking for a solution, I found the IMX6Q_GPR4_IPU_WR_CACHE_CTL / IMX6Q_GPR4_IPU_RD_CACHE_CTL bits in the reference manual.

However, these are not explained well in the documentation I have.

Is there a document somewhere explaining what these controls do?

If this bits can help me, is there a patch to freescale's linux that can help me control them (and set this memory to be cacheable) ?

Thanks,

Ofer

Re: IPU/VPU cacheable memory access

rogerio_silva — Tue, 13 Aug 2013 13:00:17 GMT

Hi Jimmy,

There is a patch that enables these caches:

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6?h=imx_3.0.35_4.0.0&id=a8d8fc28a65973a8e96777127a7de43b523e2060

Rgds

Rogerio

Re: IPU/VPU cacheable memory access

ofer_livny — Tue, 13 Aug 2013 16:23:36 GMT

Thanks Rogerio

Turns out this patch was already present in our kernel. Missed that when I was looking for GPR4 references for some reason...

Ofer