Cortex M7 GPIO toggle frequency

andrej_valek — Tue, 11 Jun 2024 13:01:35 GMT

Dear community!

I have an 8MPLUSLPD4-EVK board and wanted to control the GPIO pin inside M7 core (MIMX8ML8xxxKZ). So I took the https://github.com/nxp-mcuxpresso/mcux-sdk/ and use a led_output project as an example. I wanted to toggle GPIO pin as fast as possible. The Systemclk is running at 800MHz, but the output is toggling with freq 4MHz. I know, that the GPIO bus has to be driven lower then the syslck, but not 4MHz.

// board.h #define BOARD_SIGNAL_LOOP_GPIO GPIO3 #define BOARD_SIGNAL_LOOP_GPIO_PIN 21U // pin_mux.c void BOARD_InitPins(void) { IOMUXC_SetPinMux(IOMUXC_SAI5_RXD0_GPIO3_IO21, 0U); IOMUXC_SetPinConfig(IOMUXC_SAI5_RXD0_GPIO3_IO21, IOMUXC_SW_PAD_CTL_PAD_PE(1U) | IOMUXC_SW_PAD_CTL_PAD_DSE(3U) | IOMUXC_SW_PAD_CTL_PAD_FSEL(1U)); IOMUXC_SetPinMux(IOMUXC_UART4_RXD_UART4_RX, 0U); IOMUXC_SetPinConfig(IOMUXC_UART4_RXD_UART4_RX, IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_PE_MASK); IOMUXC_SetPinMux(IOMUXC_UART4_TXD_UART4_TX, 0U); IOMUXC_SetPinConfig(IOMUXC_UART4_TXD_UART4_TX, IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_PE_MASK); } // main.c #include "fsl_debug_console.h" #include "pin_mux.h" #include "clock_config.h" #include "board.h" int main(void) { gpt_config_t gptConfig; /* Board pin, clock, debug console init */ /* M7 has its local cache and enabled by default, * need to set smart subsystems (0x28000000 ~ 0x3FFFFFFF) * non-cacheable before accessing this address region */ BOARD_InitMemory(); /* Board specific RDC settings */ BOARD_RdcInit(); BOARD_InitBootPins(); BOARD_BootClockRUN(); BOARD_InitDebugConsole(); /* Init GPIO pins as an outputs */ gpio_pin_config_t signal_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; GPIO_PinInit(BOARD_SIGNAL_LOOP_GPIO, BOARD_SIGNAL_LOOP_GPIO_PIN, &signal_config); PRINTF("Start generating signals...\r\n"); while (1) { GPIO_PortToggle(BOARD_SIGNAL_LOOP_GPIO, 1u << BOARD_SIGNAL_LOOP_GPIO_PIN); } }

I tried multiple GPIOs, but the result is still the same.

So what's wrong here? Or the other question is, how can I verify, that the systemclk is running at 800MHz.

Thanks,
Andy

Re: Cortex M7 GPIO toggle frequency

Manuel_Salas — Wed, 12 Jun 2024 21:08:52 GMT

Hello @andrej_valek

Please refer to this thread.

Best regards,

Salas.

Re: Cortex M7 GPIO toggle frequency

andrej_valek — Thu, 13 Jun 2024 06:39:22 GMT

Thank you @Manuel_Salas ,

but this won't help me I guess.

I'm using the GPIO_PortToggle function, which reflects to

static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) { #if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) base->DR_TOGGLE = mask; #else base->DR ^= mask; #endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ }

so I guess there is no overhead. The fact (from the previous thread), that GPIO is connected to IPG_CLK_ROOT which is running at 66.66MHz won't reflect to my behavior. The output freq on that pin is 4MHz.

On the other hand, could it be that I'm touching a wrong GPIO? Or maybe, would it be possible to test it on your side or provide me an application/code for verification?

Many thanks,
Andy

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