topic Re: i.MX 7Dual_VSNVS sequence in i.MX Processors

i.MX 7Dual_VSNVS sequence

tonywk — Wed, 05 Jun 2024 02:36:09 GMT

Hi team,

The power up sequence of i.mx7 is correct with PF3000.

However, when we remove the Vin of PF3000, VSNVS would turn off faster than other power rails.

Is that a problem for i.mx7?

Thanks.

jimmychan — Mon, 10 Jun 2024 17:25:17 GMT

It is better to follow the Power down sequence.

Please read the datasheet.

4.1.10 Power-down sequence

tonywk — Wed, 12 Jun 2024 04:55:35 GMT

If the Power down sequence can not be follow, any risk would have while the power up sequence is always correct?

Thanks.

tonywk — Tue, 02 Jul 2024 05:33:14 GMT

Hi team,

Here is the measure result of i.mx7 power down sequence.

Could you advise me for following result?

Any risk it could be while the power down sequence can't be meet?

1.VDD_ARM_IN&SW2_1V8&VLDO1_1V8 get to GND to VSNVS ramp down ,the result is -23.91s. ( Power off)

2.NVCC_DRAM&DDR_VREF power down to VDD_SOC_IN power down, the result is -1.68s. ( Power off)

3.VLDO3_3V3&NVCC_3V3&NVCC_SD1 get to GND to VSNVS ramp down, the result is -2.40s. ( Power off)

4.VCC_5V&VDD_SOC_IN get to GND to VSNVS ramp down, the result is -8.49s. ( Power off)

And another question about the power down requirement of PF3000.

VDDIO would be higher than VIN within 1.31s when power off the system.

Is this requirement to be followed even in power down?

Thanks.