<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX Processors中的主题 IMX8MM DSI to LVDS Configuration</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DSI-to-LVDS-Configuration/m-p/1877481#M224307</link>
    <description>&lt;P&gt;We are using i.MX 8M Mini (imx8mm) on a SOM module.&amp;nbsp; The module includes an onboard SN65DSI84 LVDS bridge.&amp;nbsp; The bridge works with a particular display (single link LVDS 800x480), but we need to interface it with a dual-link LVDS 1920x1200 panel.&amp;nbsp; I have adjusted the dts files to enable dual-link mode and the proper panel configuration, but I get no output on the target display.&amp;nbsp; I do see some data&amp;nbsp; at least on both LVDS lanes.&amp;nbsp; I have attached relevant code snippets from the DTS files for reference.&amp;nbsp; One thing I found is that if the pixel clock is set above 150 MHz (the recommended pixel clock is 77.56 MHZ * 2 = 155.12 MHz), the framebuffer device does not appear at all in /dev/fb0 or /sys/class/graphics, so I am using the minimum panel timings for now.&lt;/P&gt;&lt;P&gt;Looking at the TI forums, there is a lot of talk about needing to set the DSI clock so the LVDS bridge can derive the LVDS pixel clock.&amp;nbsp; However, I see little to no information on how to do this on the imx8mm and no clues from the dts bindings documentation.&lt;/P&gt;&lt;P&gt;Is it necessary to manually (through dts or driver source code modification) adjust the DSI clock to meet the requirements of the LVDS panel?&amp;nbsp; Or, is the DSI clocks handled automatically based on the panel timings?&lt;/P&gt;&lt;P&gt;As a side note, I also tried to double the horizontal timings for the 800x480 display and hook it up to just 1 LVDS port.&amp;nbsp; I expected to see only odd or even pixels, but the display does not show correctly (looks like vertical stripes).&amp;nbsp; I really think there is something missing in the DSI/LVDS configuration but it seems there is not enough clear guidance on what I could be missing.&lt;/P&gt;&lt;P&gt;The DSI shenanigans on this CPU are really a big problem.&amp;nbsp; We have had no luck getting any displays working with this CPU other than pre-provided kits.&amp;nbsp; We have been trying to get the required displays working for months with no forward progress.&lt;/P&gt;&lt;P&gt;Lastly, I am working with Yocto 6.1 Mickledore release.&lt;/P&gt;</description>
    <pubDate>Wed, 29 May 2024 17:22:00 GMT</pubDate>
    <dc:creator>DPaden</dc:creator>
    <dc:date>2024-05-29T17:22:00Z</dc:date>
    <item>
      <title>IMX8MM DSI to LVDS Configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DSI-to-LVDS-Configuration/m-p/1877481#M224307</link>
      <description>&lt;P&gt;We are using i.MX 8M Mini (imx8mm) on a SOM module.&amp;nbsp; The module includes an onboard SN65DSI84 LVDS bridge.&amp;nbsp; The bridge works with a particular display (single link LVDS 800x480), but we need to interface it with a dual-link LVDS 1920x1200 panel.&amp;nbsp; I have adjusted the dts files to enable dual-link mode and the proper panel configuration, but I get no output on the target display.&amp;nbsp; I do see some data&amp;nbsp; at least on both LVDS lanes.&amp;nbsp; I have attached relevant code snippets from the DTS files for reference.&amp;nbsp; One thing I found is that if the pixel clock is set above 150 MHz (the recommended pixel clock is 77.56 MHZ * 2 = 155.12 MHz), the framebuffer device does not appear at all in /dev/fb0 or /sys/class/graphics, so I am using the minimum panel timings for now.&lt;/P&gt;&lt;P&gt;Looking at the TI forums, there is a lot of talk about needing to set the DSI clock so the LVDS bridge can derive the LVDS pixel clock.&amp;nbsp; However, I see little to no information on how to do this on the imx8mm and no clues from the dts bindings documentation.&lt;/P&gt;&lt;P&gt;Is it necessary to manually (through dts or driver source code modification) adjust the DSI clock to meet the requirements of the LVDS panel?&amp;nbsp; Or, is the DSI clocks handled automatically based on the panel timings?&lt;/P&gt;&lt;P&gt;As a side note, I also tried to double the horizontal timings for the 800x480 display and hook it up to just 1 LVDS port.&amp;nbsp; I expected to see only odd or even pixels, but the display does not show correctly (looks like vertical stripes).&amp;nbsp; I really think there is something missing in the DSI/LVDS configuration but it seems there is not enough clear guidance on what I could be missing.&lt;/P&gt;&lt;P&gt;The DSI shenanigans on this CPU are really a big problem.&amp;nbsp; We have had no luck getting any displays working with this CPU other than pre-provided kits.&amp;nbsp; We have been trying to get the required displays working for months with no forward progress.&lt;/P&gt;&lt;P&gt;Lastly, I am working with Yocto 6.1 Mickledore release.&lt;/P&gt;</description>
      <pubDate>Wed, 29 May 2024 17:22:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DSI-to-LVDS-Configuration/m-p/1877481#M224307</guid>
      <dc:creator>DPaden</dc:creator>
      <dc:date>2024-05-29T17:22:00Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MM DSI to LVDS Configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DSI-to-LVDS-Configuration/m-p/1879125#M224428</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;I think the following would be of help to you:&lt;BR /&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Only-half-display-on-a-dual-link-LVDS-LCD-1920x1080-using/m-p/118943" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Only-half-display-on-a-dual-link-LVDS-LCD-1920x1080-using/m-p/118943&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;Best regards/Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Fri, 31 May 2024 18:36:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DSI-to-LVDS-Configuration/m-p/1879125#M224428</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2024-05-31T18:36:38Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MM DSI to LVDS Configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DSI-to-LVDS-Configuration/m-p/2034782#M233405</link>
      <description>&lt;P&gt;You appear to have made a broken link to a question that has not been answered?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I am also getting similar issues and I want to know the same answers that the original poster asked. Do you need to manually configure the DSI clock?&lt;/P&gt;</description>
      <pubDate>Mon, 27 Jan 2025 20:43:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DSI-to-LVDS-Configuration/m-p/2034782#M233405</guid>
      <dc:creator>alexkl</dc:creator>
      <dc:date>2025-01-27T20:43:56Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MM DSI to LVDS Configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DSI-to-LVDS-Configuration/m-p/2034786#M233406</link>
      <description>The correct link is here: &lt;A href="https://community.nxp.com/t5/i-MX-Processors/Only-half-display-on-a-dual-link-LVDS-LCD-1920x1080-using/m-p/1189437" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Only-half-display-on-a-dual-link-LVDS-LCD-1920x1080-using/m-p/1189437&lt;/A&gt;</description>
      <pubDate>Mon, 27 Jan 2025 20:53:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DSI-to-LVDS-Configuration/m-p/2034786#M233406</guid>
      <dc:creator>alexkl</dc:creator>
      <dc:date>2025-01-27T20:53:25Z</dc:date>
    </item>
  </channel>
</rss>

