topic Re: SAI losts the first frame date (=16ch)? in i.MX Processors

SAI losts the first frame date (=16ch)?

Takashi_Kashiwagi — Thu, 16 May 2024 05:03:34 GMT

Hi community and Tech Support.

We have using I.MX8MP with yocto(kernel 5.15.71).

When receiving data using SAI, the first frame is lost.

The SAI settings are as follows.

* slave mode(TXFS, TXC, RXFS and RXC are provided by external custom codec)

* WORD LENGTH = 32bit

* Frequency = 48~768KHz

* format = left_j

* Channel = 16ch

* Lane = 8 (TXD0~7/RXD0~8)

* Slots per lane = 2

Is there any workaround?

The following is the data dumped from the first received data with snd_pcm_readi.

I'm expecting 64 bytes of data 00 00 00 00...10 00 00 00 to be included, but that part is missing.

---------------------------------
11 00 00 00 12 00 00 00 13 00 00 00 14 00 00 00 : ................
15 00 00 00 16 00 00 00 17 00 00 00 18 00 00 00 : ................
19 00 00 00 1A 00 00 00 1B 00 00 00 1C 00 00 00 : ................
1D 00 00 00 1E 00 00 00 1F 00 00 00 20 00 00 00 : ............ ...
21 00 00 00 22 00 00 00 23 00 00 00 24 00 00 00 : !..."...#...$...
25 00 00 00 26 00 00 00 27 00 00 00 28 00 00 00 : %...&...'...(...
29 00 00 00 2A 00 00 00 2B 00 00 00 2C 00 00 00 : )...*...+...,...
2D 00 00 00 2E 00 00 00 2F 00 00 00 30 00 00 00 : -......./...0...
-------------------------------------------------------------------

Best Regards

KASHIWAGI Takashi

Re: SAI losts the first frame date (=16ch)?

JorgeCas — Fri, 17 May 2024 20:05:18 GMT

Hello,

Please share me the next details about your setup:

Are you seeing this issue on playback?

Which CODEC/DSP/etc are you using?

Did you measure the signals when you receive the data?

Best regards.

Re: SAI losts the first frame date (=16ch)?

Takashi_Kashiwagi — Mon, 20 May 2024 04:28:10 GMT

Hi @JorgeCas san

Thank you for reply.

> Are you seeing this issue on playback?

No, but the playback side is still untested.

> Which CODEC/DSP/etc are you using?

I'm using custom CODEC(FPGA). The custom CODEC provides TXC/RXC and TXFS/RXFS.

At this time, data for the first 16 channels cannot be imported. Other than that, it's working mostly as intended.

> Did you measure the signals when you receive the data?

I used snd_pcm_readi with alsalib.

And I compared the data first captured with snd_pcm_readi and the waveform output by the custom CODEC (captured by an oscilloscope).

Should I check the waveform timing of RXC/RXFS?

Best Regards,

KASHIWAGI Takashi

Re: SAI losts the first frame date (=16ch)?

JorgeCas — Mon, 20 May 2024 13:49:33 GMT

Hello,

No, but the playback side is still untested.

Please try to check if the issue on playback is also present.

Should I check the waveform timing of RXC/RXFS?

Sure, please confirm that the data is correctly sent by FPGA and check timing for RXC/RXFS.

Best regards.

Re: SAI losts the first frame date (=16ch)?

Takashi_Kashiwagi — Thu, 23 May 2024 04:43:49 GMT

Hi @JorgeCas san

Thankb you for reply.

> Please try to check if the issue on playback is also present.

I confirmed. The first frame was also missing on the playback side.

> Sure, please confirm that the data is correctly sent by FPGA and check timing for RXC/RXFS.

I understand. I'm going to check it out now, but I think it will take some time due to equipment.

Best Regards

KASHIWAGI Takashi

Re: SAI losts the first frame date (=16ch)?

Takashi_Kashiwagi — Fri, 24 May 2024 02:31:04 GMT

Hi @JorgeCas san

I captured waveform of RXC/RXFS/RXD with oscilloscope. I send the file.

* SAI1_RXFS_RXC_RXD0_最初周期_20240524.png

* SAI1_RXFS_RXC_RXD0_最初半周期_20240524.png

I noticed that the duty ratio of the RXC is strange. We will fix this issue later.
Is there anything else suspicious?

Best Regards,

KASHIWAGI Takashi

Re: SAI losts the first frame date (=16ch)?

JorgeCas — Fri, 24 May 2024 13:42:22 GMT

Hello @Takashi_Kashiwagi,

Thank you for the update.

I do not have additional suspicious for this issue, please let me know if solving duty ratio of the RXC helps with your issue.

Best regards.

Re: SAI losts the first frame date (=16ch)?

Takashi_Kashiwagi — Tue, 28 May 2024 02:33:48 GMT

Hi @JorgeCas san

Thank you for reply

> please let me know if solving duty ratio of the RXC helps with your issue.

It's hard to tell from the image, but the RXC duty ratio was over 40-60%. It's working so far, but it's out of spec, so I'll fix it.
However, I don't think this fix will solve the problem of missing the first frame.

Are there any stricter timing requirements for RXFS and RXC when SAI starts operating?

Best Regards,

KASHIWAGI Takashi

Re: SAI losts the first frame date (=16ch)?

JorgeCas — Tue, 28 May 2024 14:24:27 GMT

Hello,

To check timing requirements, I suggest you take a look in datasheet chapter 3.8.13 "SAI/I2S switching specifications".

Best regards.

Re: SAI losts the first frame date (=16ch)?

Takashi_Kashiwagi — Fri, 31 May 2024 02:07:35 GMT

Hi @JorgeCas san

Thank you for reply!

I checked the RXC/RXFS timing in "Table 68. Slave mode SAI timing" and there seem to be no problems with the timing other than "S12 SAI_BCLK pulse width high/low (input)".

Have you seen any other cases where the first frame of SAI is dropped?

Or is this the way the IMX8MP SAI is supposed to behave?

Best Regards,

KASHIWAGI Takashi

Re: SAI losts the first frame date (=16ch)?

Takashi_Kashiwagi — Fri, 14 Jun 2024 01:51:06 GMT

Hi community!

This phenomenon was due to the SoC specifications.

According to I.MX8MP Reference Manual,

14.4.2.3 Frame sync configuration
When enabled, the SAI continuously transmits and/or receives frames of data. Each
frame consists of a fixed number of words and each word consists of a fixed number of
bits. Within each frame, any given word can be masked causing the receiver to ignore
that word and the transmitter to tri-state for the duration of that word.
The frame sync signal indicates the start of each frame. A valid frame sync requires a
rising edge (if active high) or falling edge (if active low) to be detected and the
transmitter or receiver cannot be busy with a previous frame. A valid frame sync is also
ignored (slave mode) or not generated (master mode) for the first four bit clock cycles
after enabling the transmitter or receiver.

Best Regards,

KASHIWAGI Takashi