topic Re: IMX8M PLUS MIPI_DSI register in i.MX Processors

IMX8M PLUS MIPI_DSI register

flashever — Mon, 06 May 2024 10:36:32 GMT

I found MIPI_DSI register description in imx8 m plus reference manual chapter 13.6.9.1, but no more details about these register setting. where can I get these setting details? For example, different value I set to M_THSPRPRCTL will cause what kind of result?

Re: IMX8M PLUS MIPI_DSI register

JorgeCas — Mon, 06 May 2024 15:12:58 GMT

Hello,

We don't have specific register information, even on MIPI D-PHY IP spec, Samsung doesn't describe them, for timing registers. Customers doesn't need calculate the timing by themselves this is defined on drivers.

Best regards.

Re: IMX8M PLUS MIPI_DSI register

flashever — Wed, 08 May 2024 01:18:44 GMT

Thanks. Our Data Lane HS-TX 20%-80% Rise/Fall Time is too slow in MIPI D-PHY SI test. Are there any resister setting can increase TX drive capacity or slew rate?

Re: IMX8M PLUS MIPI_DSI register

JorgeCas — Wed, 08 May 2024 13:35:12 GMT

Hello,

The register Master and Slave DPHY Control Low Register in chapter 13.2.3.1.10 of reference manual mentions HS-TX Rise and Fall Time Control bit field that could be helpful for you.

Best regards.

Re: IMX8M PLUS MIPI_DSI register

flashever — Thu, 09 May 2024 03:21:29 GMT

Hello,

I tried to change value of HS_TX_RISE_FALL_TIME_CTL register to 011b-120mV and 100b-230mV, found rise/fall time has no change.

I also enabled HS_TX_SLEW_RATE_EN and change HS_TX_SLEW_RATE_CTL to 000 and 111, rise/fall time has no change.