<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: How change the PLL2_PFD0 frequency under Linux OS</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1859411#M223312</link>
    <description>&lt;P&gt;Hello, Anybody can give a help on the above new findings? Thanks a lot for the support.&lt;/P&gt;</description>
    <pubDate>Mon, 06 May 2024 06:22:39 GMT</pubDate>
    <dc:creator>mzl</dc:creator>
    <dc:date>2024-05-06T06:22:39Z</dc:date>
    <item>
      <title>How change the PLL2_PFD0 frequency under Linux OS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1834439#M221724</link>
      <description>&lt;P&gt;On my PCBA design based on i.MX6ULL. the base system is Linux OS.&lt;/P&gt;&lt;P&gt;Now we measured the DDR frequency with Oscilloscope and confirmed it's 307MHz. Then we read the register's value of CBCDR, CBCMR and&amp;nbsp;CCM_ANALOG_PFD_528n and got the following value:&lt;/P&gt;&lt;P&gt;Value at address 0x20C4014 (0x76fc6014): 0x98D00&lt;/P&gt;&lt;P&gt;Value at address 0x20C4018 (0x76f80018): 0x24429324&lt;/P&gt;&lt;P&gt;Value at address 0x20C8100 (0x76fed100): 0xD018D05F&lt;/P&gt;&lt;P&gt;Value at address 0x20C8104 (0x76f9c104): 0xD0D8D05F&lt;/P&gt;&lt;P&gt;Value at address 0x20C8108 (0x76fc9108): 0xD098D05F&lt;/P&gt;&lt;P&gt;Value at address 0x20C810C (0x76f0c10c): 0xD098D05F&lt;/P&gt;&lt;P&gt;From the above registers' values, the DDR clock derived from PLL2_PFD0, and the PLL2_PFD0 frequency is 307MHz, which means that the DDR clock frequency is also configured to be 307MHz, the measured frequency from Oscilloscope matches the register configuration.&lt;/P&gt;&lt;P&gt;Now we want to improve the PLL2_PFD0 to be 396MHz so that the DDR clock frequency can be raised to 396MHz, in Linux system, how can we change the PLL2_PFD0 frequency? Thanks.&lt;/P&gt;</description>
      <pubDate>Mon, 25 Mar 2024 08:44:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1834439#M221724</guid>
      <dc:creator>mzl</dc:creator>
      <dc:date>2024-03-25T08:44:45Z</dc:date>
    </item>
    <item>
      <title>Re: How change the PLL2_PFD0 frequency under Linux OS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1835322#M221795</link>
      <description>&lt;P&gt;in linux kernel, the pll is defined in the clock driver&lt;/P&gt;
&lt;P&gt;&lt;A href="https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/clk/imx/clk-imx6ul.c" target="_blank"&gt;https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/clk/imx/clk-imx6ul.c&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;hws[IMX6UL_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);&lt;BR /&gt;hws[IMX6UL_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);&lt;BR /&gt;hws[IMX6UL_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);&lt;BR /&gt;hws[IMX6UL_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 26 Mar 2024 09:20:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1835322#M221795</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2024-03-26T09:20:21Z</dc:date>
    </item>
    <item>
      <title>Re: How change the PLL2_PFD0 frequency under Linux OS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1857146#M223135</link>
      <description>&lt;P&gt;Hello, from the clock tree read from our PCBA. Now we got the following values:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="clock tree read.PNG" style="width: 928px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/276558i0C5A011C42C6601D/image-size/large?v=v2&amp;amp;px=999" role="button" title="clock tree read.PNG" alt="clock tree read.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;The value 306580645 actually matches with the DDR frequency measured on our PCBA (about 307MHz).&lt;/P&gt;&lt;P&gt;So my question is: where could I change this value? Thanks a lot.&lt;/P&gt;</description>
      <pubDate>Tue, 30 Apr 2024 02:42:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1857146#M223135</guid>
      <dc:creator>mzl</dc:creator>
      <dc:date>2024-04-30T02:42:17Z</dc:date>
    </item>
    <item>
      <title>Re: How change the PLL2_PFD0 frequency under Linux OS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1859411#M223312</link>
      <description>&lt;P&gt;Hello, Anybody can give a help on the above new findings? Thanks a lot for the support.&lt;/P&gt;</description>
      <pubDate>Mon, 06 May 2024 06:22:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1859411#M223312</guid>
      <dc:creator>mzl</dc:creator>
      <dc:date>2024-05-06T06:22:39Z</dc:date>
    </item>
    <item>
      <title>Re: How change the PLL2_PFD0 frequency under Linux OS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1859419#M223313</link>
      <description>&lt;P&gt;Could anybody give some help on the new findings? Thanks a lot for the support.&lt;/P&gt;</description>
      <pubDate>Mon, 06 May 2024 06:25:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1859419#M223313</guid>
      <dc:creator>mzl</dc:creator>
      <dc:date>2024-05-06T06:25:59Z</dc:date>
    </item>
    <item>
      <title>Re: How change the PLL2_PFD0 frequency under Linux OS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1891885#M225321</link>
      <description>&lt;P&gt;pls refer to the link&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/iMX6-how-to-change-DDR-PFD-frequency/m-p/883193" target="_blank"&gt;Solved: iMX6 - how to change DDR PFD frequency - NXP Community&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/engineering-bulletin/EB790.pdf?_gl=1*14rlwqx*_ga*NjE2MDU4NDc0LjE3MTgyNTIyNTI.*_ga_WM5LE0KMSH*MTcxODk0NzkyNi4xMy4xLjE3MTg5NDk4NjYuMC4wLjA." target="_blank"&gt;Configuration of Phase Fractional Dividers (nxp.com)&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 21 Jun 2024 06:07:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-change-the-PLL2-PFD0-frequency-under-Linux-OS/m-p/1891885#M225321</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2024-06-21T06:07:16Z</dc:date>
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  </channel>
</rss>

