topic Re: SPL code, pmic_stby_req in i.MX Processors

SPL code, pmic_stby_req

sbmd_1234 — Mon, 29 Apr 2024 06:09:39 GMT

Hi

I have read the spl.c code inside power_init_board() function reg_write is happening as :

/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);

/* enable DVS control through PMIC_STBY_REQ */
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);

So, what i understood is like in every board bootup register write of DVS controlling through pmic_stby_req is configured of PMIC.

But my question is how the system is getting triggered when the imx93 is sending standby request?

Re: SPL code, pmic_stby_req

Manuel_Salas — Wed, 01 May 2024 16:24:14 GMT

Hello @sbmd_1234

When the PMIC receives the standby request signal PMIC_STBY_REQ it interprets this signal as a request to transition the system into a low-power state.

Also you can check the reference manual, look the PMIC standby control (PMIC_CTRL) register and PMIC standby pre delay control (PMIC_PRE_DLY_CTRL).

Best regards.

Re: SPL code, pmic_stby_req

sbmd_1234 — Wed, 01 May 2024 16:37:04 GMT

Hi @Manuel_Salas

Thanks for your reply!!

Actually, I can see the system gets voltage down by the PMIC i.e ( BUCK1_VOUT_DVS1 reg) during booting time but the question is may be somewhere system checks the low power mode conditions so can we read those conditions.

If those conditions are checked for standby then what is that process?