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    <title>topic Re: IMX8MP ARC &amp;lt;-&amp;gt; eARC transition in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1852643#M222867</link>
    <description>&lt;P&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;I researched internally but we do not have a solution that implements that ARC/eARC transition automatically.&lt;/P&gt;
&lt;P&gt;According to reference manual the different operating modes are configured with the next interrupts:&lt;/P&gt;
&lt;P&gt;- eARC RX mode: In order to set up the AUDIO_XCVR in eARC_RX mode, load the M0 code and release it from reset. Once HPD is received, FW will enable the PHY and set up the PLL as needed.&lt;/P&gt;
&lt;P&gt;- ARC RX mode: In order to set up the PHY and controller in ARC RX mode, assert the ARC single ended mode (IER[23]) or ARC common mode (IER[22]) interrupt. When either of these interrupts are asserted, FW will program the PHY and Controller controller registers.&lt;/P&gt;
&lt;P&gt;- SPDIF TX mode: Host core will need to program the PHY PLL to output a 2*TX bit rate clock or 10*TX bit rate clock based on selection programmed in TX_DATAPATH_CTRL[10].&lt;/P&gt;
&lt;P&gt;- SPDIF RX mode: This mode can be set up using IER[20]. This will set up the PHY and Controller registers as needed. SPDIF TX and RX can be operated simultaneously. If this is desired, use IER[19]. The HDMI TX SS PLL will still need to be set up by the host core.&lt;/P&gt;
&lt;P&gt;Maybe this information could be helpful to determinate your desired transition of your design.&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
    <pubDate>Tue, 23 Apr 2024 15:40:16 GMT</pubDate>
    <dc:creator>JorgeCas</dc:creator>
    <dc:date>2024-04-23T15:40:16Z</dc:date>
    <item>
      <title>IMX8MP ARC &lt;-&gt; eARC transition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1849952#M222706</link>
      <description>&lt;P&gt;Hello NXP&lt;/P&gt;&lt;P&gt;I have recently gotten HPD + DDC + CEC + ARC/eARC&amp;nbsp; up and running using following components:&lt;/P&gt;&lt;P&gt;- fsl_xcvr.* driver.&lt;/P&gt;&lt;P&gt;- cec-ctl --audio&lt;/P&gt;&lt;P&gt;- cec-follower&lt;/P&gt;&lt;P&gt;- amixer - e.g. :&lt;/P&gt;&lt;PRE&gt;amixer &lt;SPAN class=""&gt;-c&lt;/SPAN&gt; imxaudioxcvr cset &lt;SPAN class=""&gt;numid&lt;/SPAN&gt;&lt;SPAN class=""&gt;=&lt;/SPAN&gt;1,iface&lt;SPAN class=""&gt;=&lt;/SPAN&gt;MIXER,name&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;SPAN class=""&gt;'XCVR Mode'&lt;/SPAN&gt; &lt;SPAN class=""&gt;'ARC RX'&amp;nbsp;or&amp;nbsp;"eARC"&lt;/SPAN&gt;&lt;/PRE&gt;&lt;P&gt;- gst-launch for routing sound to I2S output - but with 2 different pipeline setup for "ARC" and "eARC".&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;This on linux 5.15.71&lt;/P&gt;&lt;P&gt;--------&lt;/P&gt;&lt;P&gt;However I am now in a state where I cannot easily determine whenever user makes a manual transition(selection) between ARC and eARC on TV. And also I have to stop Gstreamer pipeline for re-configuring the driver for ARC or eARC (amixer).&amp;nbsp;&lt;/P&gt;&lt;P&gt;On dedicated eARC chips like&amp;nbsp;sii9437 I used to ask the chip about the "eARC link state".&lt;/P&gt;&lt;P&gt;In the code implemented in fsl_xcvr.c it seems only related code is that I get an interrupt if eARC link has failed:&amp;nbsp;irq0_isr(): FSL_XCVR_IRQ_ARC_MODE. Maybe this information is available in status interrupt which seems not to be implemented in fsl_xcvr.&lt;/P&gt;&lt;P&gt;Can you maybe help me with any ideas how to achieve my goal - here are some questions for which answers could help me on the way:&lt;/P&gt;&lt;P&gt;- Basically: I want to automatically runtime change mode between ARC and eARC whenever TV wants this - have you tried this?&amp;nbsp;&lt;/P&gt;&lt;P&gt;- Does the firmware of xcvr fully support the transition between "ARC", "DISCx", "IDLEx" &amp;amp; "eARC" as of HDMI specification&amp;nbsp; ("HPD" + "COMMA") with an easy way to coordinate this with e.g. cec-follower etc?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;- Would you have some more detailed design-notes / unit-test to support this?&lt;/P&gt;&lt;P&gt;- Is there a better way to route Audio from XCVR to I2S other than Gstreamer?&lt;/P&gt;&lt;P&gt;- Are there any plans to expand the functionality of fsl_xcvr with e.g. status information or HDMI state (DISC, IDLE etc.)?&amp;nbsp;&lt;/P&gt;&lt;P&gt;- Any other information would help?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The good thing is that I have the audio pipeline working on both ARC and eARC just need a smooth transition.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind Regards Flemming&lt;/P&gt;</description>
      <pubDate>Thu, 18 Apr 2024 17:12:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1849952#M222706</guid>
      <dc:creator>robot1</dc:creator>
      <dc:date>2024-04-18T17:12:53Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MP ARC &lt;-&gt; eARC transition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1852643#M222867</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;I researched internally but we do not have a solution that implements that ARC/eARC transition automatically.&lt;/P&gt;
&lt;P&gt;According to reference manual the different operating modes are configured with the next interrupts:&lt;/P&gt;
&lt;P&gt;- eARC RX mode: In order to set up the AUDIO_XCVR in eARC_RX mode, load the M0 code and release it from reset. Once HPD is received, FW will enable the PHY and set up the PLL as needed.&lt;/P&gt;
&lt;P&gt;- ARC RX mode: In order to set up the PHY and controller in ARC RX mode, assert the ARC single ended mode (IER[23]) or ARC common mode (IER[22]) interrupt. When either of these interrupts are asserted, FW will program the PHY and Controller controller registers.&lt;/P&gt;
&lt;P&gt;- SPDIF TX mode: Host core will need to program the PHY PLL to output a 2*TX bit rate clock or 10*TX bit rate clock based on selection programmed in TX_DATAPATH_CTRL[10].&lt;/P&gt;
&lt;P&gt;- SPDIF RX mode: This mode can be set up using IER[20]. This will set up the PHY and Controller registers as needed. SPDIF TX and RX can be operated simultaneously. If this is desired, use IER[19]. The HDMI TX SS PLL will still need to be set up by the host core.&lt;/P&gt;
&lt;P&gt;Maybe this information could be helpful to determinate your desired transition of your design.&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Tue, 23 Apr 2024 15:40:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1852643#M222867</guid>
      <dc:creator>JorgeCas</dc:creator>
      <dc:date>2024-04-23T15:40:16Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MP ARC &lt;-&gt; eARC transition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1855606#M223042</link>
      <description>&lt;P&gt;Thanks Jorge&lt;/P&gt;&lt;P&gt;I found the referred section of reference manual:&lt;BR /&gt;14.6.2.3 Functional Operating mode...&lt;/P&gt;&lt;P&gt;Seems like the handling of "single ended" / "common mode" is what can help me right now:&lt;BR /&gt;&lt;BR /&gt;static const u32 fsl_xcvr_phy_arc_cfg[] = {&lt;BR /&gt;FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;#define FSL_XCVR_ISR_SET_ARC_CM_INT BIT(22)&lt;BR /&gt;#define FSL_XCVR_ISR_SET_ARC_SE_INT BIT(23)&lt;/P&gt;&lt;P&gt;Above defines are not used anywhere in c file.&lt;/P&gt;&lt;P&gt;And then I may probably have to add some intelligence myself...&lt;/P&gt;&lt;P&gt;-----&lt;/P&gt;&lt;P&gt;Would it be possible to get the current state of ARC / eARC functionallity: "IDLE1", "DISC1", "IDLE2", "DISC2", "ARC", "eARC"?&lt;/P&gt;&lt;P&gt;Because timing is everything with this...&lt;/P&gt;&lt;P&gt;Kind regards Flemming&lt;/P&gt;</description>
      <pubDate>Fri, 26 Apr 2024 10:42:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1855606#M223042</guid>
      <dc:creator>robot1</dc:creator>
      <dc:date>2024-04-26T10:42:21Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MP ARC &lt;-&gt; eARC transition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1855863#M223057</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;I researched on documentation if there is a register to get de state of ARC/eARC functionality but the most similar is the next, maybe could be helpful for your application.&lt;/P&gt;
&lt;P&gt;The register "&lt;STRONG&gt;Interrupt enables for interrupt n&lt;/STRONG&gt;" (EXT_IERx), has the next bit field:&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;ARC_MODE_IE _n&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;Interrupt to indicate ARC mode setup.&lt;/P&gt;
&lt;P&gt;This interrupt enables SEL_ARC_MODE interrupt indicating eARC RX state machine could not establish a heartbeat. Check to see if ARC mode needs to be set up.&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Fri, 26 Apr 2024 16:55:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1855863#M223057</guid>
      <dc:creator>JorgeCas</dc:creator>
      <dc:date>2024-04-26T16:55:03Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MP ARC &lt;-&gt; eARC transition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1857557#M223174</link>
      <description>Thanks Jorge&lt;BR /&gt;&lt;BR /&gt;I see there are some work to do here:-)&lt;BR /&gt;&lt;BR /&gt;I will try to combine the different information and make my own "state machine awareness" on top of that.&lt;BR /&gt;&lt;BR /&gt;Thanks Flemming</description>
      <pubDate>Tue, 30 Apr 2024 12:45:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ARC-lt-gt-eARC-transition/m-p/1857557#M223174</guid>
      <dc:creator>robot1</dc:creator>
      <dc:date>2024-04-30T12:45:40Z</dc:date>
    </item>
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