i.MX ProcessorsのトピックRe: i.MX8Nano compactible RAM

i.MX8Nano compactible RAM

Rajanand — Mon, 22 Apr 2024 14:04:48 GMT

As a student exploring the i.MX8 series processor platform, I'm facing a challenge in selecting the right RAM for my application. After consulting @jan_spurek 's RAM selection guide, I decided on the MT53E1G32D2FW-046 (1Gx32) 4GB module for my i.MX8Nano design. I would appreciate it if you could validate this RAM choice or provide guidance on the key aspects and specifications to consider for RAM selection if it's not compatible.

Re: i.MX8Nano compactible RAM

jan_spurek — Mon, 22 Apr 2024 14:09:09 GMT

Hi Rajanand,

thank you for the question. Please attach the respective datasheet of the selected memory device so compatibility could be checked in more detail.

From the available information, the selected device appears to have 32-bit wide data bus while i.MX8MNano only has 16-bit DRAM data bus. This is not a big functional problem in case of LPDDR4 as the 32-bit wide devices consist of two independent 16-bit channels and only one of them can be used. However, you would only be able to access half of its density - so only 2 out of 4 GB would be available. From this reason, it looks more practical to look for 16-bit LPDDR4 devices.

Best Regards,

Jan

Re: i.MX8Nano compactible RAM

Rajanand — Mon, 22 Apr 2024 14:17:56 GMT

@jan_spurek Thank you,
well in that case this RAM should be suitable for IMX8PLUS designs right. As you mentioned that the RAM should be LPDDR4 or LPDDR4/LPDDR4X. But not LPDDR4X alone.

So, I guess this RAM satisfies the condition and is there anything else I need to consider making the design to work properly?

Re: i.MX8Nano compactible RAM

jan_spurek — Tue, 23 Apr 2024 05:47:40 GMT

Hi Rajanand,

well in that case this RAM should be suitable for IMX8PLUS designs right. As you mentioned that the RAM should be LPDDR4 or LPDDR4/LPDDR4X. But not LPDDR4X alone.

Yes, that is correct.

So, I guess this RAM satisfies the condition and is there anything else I need to consider making the design to work properly?

Yes, just with the DRAM bus width caveat in case of i.MX8MNano. For more considerations regarding the design, please refer to the Hardware Developer's Guide.

Best Regards,

Jan