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    <title>i.MX ProcessorsのトピックRe: Misleading LPDDR4 size in NXP DDR Tool</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1846261#M222450</link>
    <description>&lt;P&gt;Hello Salas,&lt;/P&gt;&lt;P&gt;thank you for responding.&lt;/P&gt;&lt;P&gt;I tried with the Config Tools v15 (selected CPU, completed in the fields in DDRC-Tab, exported .ds and lpppdr4_timing.c file).&lt;/P&gt;&lt;P&gt;The StressTestTool still reports the 'incorrect' LPDDR-size 1536MB (instead of 3072), U-Boot is running, Linux doesn't start.&lt;/P&gt;&lt;P&gt;Could there be an issue with the "Number of ROW-Adresses"?&lt;/P&gt;&lt;P&gt;The '&lt;SPAN class=""&gt;MT53E768M32D2ZW-46' data sheet reports R[16:0], the ExcelSheet blocks &amp;gt;16, in ConfigTool we tried 17, but it doesn't change the reported LPDDR-size&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="MT53E768M32D2_micrin_dataSheet.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/273484iA96649B52CB1F2B0/image-size/medium?v=v2&amp;amp;px=400" role="button" title="MT53E768M32D2_micrin_dataSheet.png" alt="MT53E768M32D2_micrin_dataSheet.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;N. Wiedmann&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 12 Apr 2024 17:18:54 GMT</pubDate>
    <dc:creator>NWiedmann</dc:creator>
    <dc:date>2024-04-12T17:18:54Z</dc:date>
    <item>
      <title>Misleading LPDDR4 size in NXP DDR Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1845189#M222388</link>
      <description>&lt;P&gt;Hello NXP-Team, hello Forum,&lt;/P&gt;&lt;P&gt;we have a custom addapted iMX8mq-based board with 3G, running&amp;nbsp;without any complains.&lt;/P&gt;&lt;P&gt;Due to a LPDDR-memory &lt;SPAN class=""&gt;discontinuation, we changed our LPDDR-Memory.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;Current LPDDR is: MT53B768M32D4NQ-062&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;New LPDDR is: MT53E768M32D2ZW-46 &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;A title="Micron MT53E768M32D2ZW-046" href="https://www.farnell.com/datasheets/4000640.pdf" target="_self"&gt;https://www.farnell.com/datasheets/4000640.pdf&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;We rerun the DDR-StressTest to configure the correct parameters of our new LPDDR&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="MT53E768M32D2_Micon_diagramm.png" style="width: 611px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/273177i48F079388E64B300/image-size/large?v=v2&amp;amp;px=999" role="button" title="MT53E768M32D2_Micon_diagramm.png" alt="MT53E768M32D2_Micon_diagramm.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;The new LPDDR size is indicated in Excel sheet as expected with 24Gb &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="MT53E768M32D2_configExcel.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/273173i45AD723564A98DC6/image-size/medium?v=v2&amp;amp;px=400" role="button" title="MT53E768M32D2_configExcel.png" alt="MT53E768M32D2_configExcel.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;But after loading the exported DDR-Script into NXP DDR Tool, the LPDDR size is announced with 1576MB.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="MT53E768M32D2_NXP-DDR-Tool.png" style="width: 380px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/273174i423CA7D426374DE3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="MT53E768M32D2_NXP-DDR-Tool.png" alt="MT53E768M32D2_NXP-DDR-Tool.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;We expeted 3072MB per Controller / of the board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;The DDR Stresstest is completed successfully, the Memory can be accessed up to the 3GB adresses within DDR-Tool (0x40000000 to 0xFF000000), &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;In U-Boot, where we changed only the adapted DDR-Setting (code exported from DDR-Tool), runs without any Problem. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;But Linux boot fails (U-Boot's "Starting kernel ...." is the last reported info)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;What is the reason of the unexpected 1536MB memory announcment in DDR Tool, which is not according to the 3GB announced by MX8M-RPA-Excel sheet?&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;Is there a misconfiguration, leading to the linux start failure?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;We are using i.MX 8M Family DDR Register Programming Aid (RPA), v33.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;Thank you for all your efforts&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;N. Wiedmann&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 11 Apr 2024 12:47:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1845189#M222388</guid>
      <dc:creator>NWiedmann</dc:creator>
      <dc:date>2024-04-11T12:47:44Z</dc:date>
    </item>
    <item>
      <title>Re: Misleading LPDDR4 size in NXP DDR Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1845336#M222404</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/232128"&gt;@NWiedmann&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Could you please try to do the same but with the Config Tools v15 software?&lt;/P&gt;
&lt;P&gt;I will attach the user guide.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please let me know how it was.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Salas.&lt;/P&gt;</description>
      <pubDate>Thu, 11 Apr 2024 16:07:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1845336#M222404</guid>
      <dc:creator>Manuel_Salas</dc:creator>
      <dc:date>2024-04-11T16:07:18Z</dc:date>
    </item>
    <item>
      <title>Re: Misleading LPDDR4 size in NXP DDR Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1846261#M222450</link>
      <description>&lt;P&gt;Hello Salas,&lt;/P&gt;&lt;P&gt;thank you for responding.&lt;/P&gt;&lt;P&gt;I tried with the Config Tools v15 (selected CPU, completed in the fields in DDRC-Tab, exported .ds and lpppdr4_timing.c file).&lt;/P&gt;&lt;P&gt;The StressTestTool still reports the 'incorrect' LPDDR-size 1536MB (instead of 3072), U-Boot is running, Linux doesn't start.&lt;/P&gt;&lt;P&gt;Could there be an issue with the "Number of ROW-Adresses"?&lt;/P&gt;&lt;P&gt;The '&lt;SPAN class=""&gt;MT53E768M32D2ZW-46' data sheet reports R[16:0], the ExcelSheet blocks &amp;gt;16, in ConfigTool we tried 17, but it doesn't change the reported LPDDR-size&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="MT53E768M32D2_micrin_dataSheet.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/273484iA96649B52CB1F2B0/image-size/medium?v=v2&amp;amp;px=400" role="button" title="MT53E768M32D2_micrin_dataSheet.png" alt="MT53E768M32D2_micrin_dataSheet.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;N. Wiedmann&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 12 Apr 2024 17:18:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1846261#M222450</guid>
      <dc:creator>NWiedmann</dc:creator>
      <dc:date>2024-04-12T17:18:54Z</dc:date>
    </item>
    <item>
      <title>Re: Misleading LPDDR4 size in NXP DDR Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1846440#M222455</link>
      <description>&lt;P&gt;Hi Sir,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;i.MX8M Quad&amp;nbsp; only support ROW=16&lt;/P&gt;&lt;P&gt;You can see this link&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Quad-8M-Mini-8M-Nano-8M-Plus-LPDDR4-DDR4-and-DDR3L/ta-p/1434761" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Quad-8M-Mini-8M-Nano-8M-Plus-LPDDR4-DDR4-and-DDR3L/ta-p/1434761&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 13 Apr 2024 03:25:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1846440#M222455</guid>
      <dc:creator>Danube</dc:creator>
      <dc:date>2024-04-13T03:25:30Z</dc:date>
    </item>
    <item>
      <title>Re: Misleading LPDDR4 size in NXP DDR Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1851810#M222829</link>
      <description>&lt;P&gt;Thank you, that is the reason for the incompatibility of the &lt;SPAN class=""&gt;MT53E768M32D2ZW-46 &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;The LPDDR needs 17 row bits to address its number of 98304 rows&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="MT53E768M32D2_micron_rowSize.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/275071i170F9E5DF7CE7980/image-size/large?v=v2&amp;amp;px=999" role="button" title="MT53E768M32D2_micron_rowSize.png" alt="MT53E768M32D2_micron_rowSize.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;According to the linked '&lt;SPAN class=""&gt;memory compatibility guide'&lt;/SPAN&gt;, the i.MX 8M Quad is limited to 16 row bits.&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;N. Wiedmann&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 22 Apr 2024 17:55:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Misleading-LPDDR4-size-in-NXP-DDR-Tool/m-p/1851810#M222829</guid>
      <dc:creator>NWiedmann</dc:creator>
      <dc:date>2024-04-22T17:55:51Z</dc:date>
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