i.MX Processors中的主题 Re: MIPI-CSI2 on Imx8MP

MIPI-CSI2 on Imx8MP

naveenprasath_0 — Wed, 11 Jan 2023 14:15:49 GMT

Hi,

We've a custom FPGA interfaced with imx8mp through MIPI-CSI2 interface. This fpga just sends out color bars at the moment for testing purposes. The data lane width is 2 and the video is YUV422 640x480 30fps. We've modified the OV5640 driver to make sure that i2c transfers are returned successfully to avoid any failures while loading.

However,we are able to observe only split color bars (with colors not properly aligned) when we capture using gstreamer. Screenshot is attached below

Quick analysis of dmesg shows that the pixclock values are filled with high negative numbers. Please refer to dmesg.txt

I'm not sure why this happens and how to set it apart from the dts and how do we verify the pix clock is set properly.

Can you please help?

Re: MIPI-CSI2 on Imx8MP

jimmychan — Tue, 17 Jan 2023 07:28:42 GMT

Beside the setting in the dts/dtsi file, you may need to check/modify the driver source code. For the details of the drivers, please read the i.MX Linux Reference Manual.

We have different version of Linux BSP.

https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX

Please download the i.MX Linux Reference Manual according to the version that you are using.

Re: MIPI-CSI2 on Imx8MP

zoro_li — Mon, 08 Apr 2024 15:09:49 GMT

For YUV422 input, do imx8mp need any special modifications?