https://community.nxp.com/t5/i-MX-Processors/imx8mp-ecspi-miso-runtime-correction/m-p/1824286#M220984 <P>Hi <a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/230671">@martmanmtx</a>!<BR />Thank you for contacting NXP Support!<BR /><BR />By hardware, our IP doesn't have that feature but you can refer to our Linux Reference Manual, maybe you can implement the feature on software modifying our driver.<BR /><BR />Sorry for the mistake!<BR /><BR />Best Regards!<BR />Chavira</P> Fri, 08 Mar 2024 16:26:39 GMT Chavira 2024-03-08T16:26:39Z https://community.nxp.com/t5/i-MX-Processors/imx8mp-ecspi-miso-runtime-correction/m-p/1824095#M220966 <P>we are using ecspi2 on ima8mp to connect extern ADC. if running spi on rather high speeds (20MHz) we have a runtime between SCLK and MISO of ~3 bits caused by ADUM1401 for galvanic insulation. i know from renesas rz/t1 we use in other system that there is a configurable runtime correction for MISO compared to SCLK that is great for handling such issues.</P><P>I searched the imx8mp manual but did not find something like this. is there a possibility to have that on imx8mp, of playing arround with polarity and phase does not help anymore?</P> Fri, 08 Mar 2024 10:44:14 GMT https://community.nxp.com/t5/i-MX-Processors/imx8mp-ecspi-miso-runtime-correction/m-p/1824095#M220966 martmanmtx 2024-03-08T10:44:14Z https://community.nxp.com/t5/i-MX-Processors/imx8mp-ecspi-miso-runtime-correction/m-p/1824286#M220984 <P>Hi <a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/230671">@martmanmtx</a>!<BR />Thank you for contacting NXP Support!<BR /><BR />By hardware, our IP doesn't have that feature but you can refer to our Linux Reference Manual, maybe you can implement the feature on software modifying our driver.<BR /><BR />Sorry for the mistake!<BR /><BR />Best Regards!<BR />Chavira</P> Fri, 08 Mar 2024 16:26:39 GMT https://community.nxp.com/t5/i-MX-Processors/imx8mp-ecspi-miso-runtime-correction/m-p/1824286#M220984 Chavira 2024-03-08T16:26:39Z