i.MX ProcessorsのトピックRe: How to use STC_RIL_SetInterleave function in SCFW

How to use STC_RIL_SetInterleave function in SCFW

luozhu — Tue, 20 Feb 2024 09:00:59 GMT

My board is imx8qm-mek,It has two DDRC.I found that the default interleaving size for A-core CPUs accessing DDR memory is 4KB. That is, the first 4KB is accessed through DDRC0 and the second 4KB is accessed through DDRC1. I want to change this size to 8KB. I found that the STC_RIL_SetInterleave function in the SCFW seems to achieve my requirement. I called STC_RIL_SetInterleave(STC10, kSTC_Interleave8K); in the board_init_ddr function, but it didn't work. Can you help me understand how to use this function?

Re: How to use STC_RIL_SetInterleave function in SCFW

Zhiming_Liu — Wed, 28 Feb 2024 00:37:16 GMT

Hi @luozhu

The STC_RIL_SetInterleave function is used in build_mx8qm_b0/soc/MX8QM/soc.o, the soc.c it's not open source. We don't recommend you modify it. If you still need to modify it. You can use like this.

STC_Type *bases[] = STC_BASE_PTRS;

for(int i; i < STC_count; i ++)

{

STC_Type *base = bases[i]

STC_RIL_SetInterleave(base, <your stc config>)

}

Re: How to use STC_RIL_SetInterleave function in SCFW

luozhu — Wed, 28 Feb 2024 13:56:32 GMT

@Zhiming_Liu

Thanks,but where can i do this in src/scfw_export_mx8qm_b0/platform/board/mx8qm_mek/board.c file?

Re: How to use STC_RIL_SetInterleave function in SCFW

wangbo9105 — Tue, 04 Jun 2024 09:04:45 GMT

Hi,@Zhiming_Liu

I also have a similar problem on the IMX8 board. I want to disable the memory interleaving mode.

How can I modify it in the source code? I don't know where to modify to make it work?

My question link is as follows:

https://community.nxp.com/t5/i-MX-Processors/How-to-modify-or-disable-the-memory-interleaving-access-mode-on/m-p/1876137#M224241

Looking forward to your reply

Re: How to use STC_RIL_SetInterleave function in SCFW

wangbo9105 — Wed, 05 Jun 2024 10:45:47 GMT

Hi,@Zhiming_Liu

The code I wrote are as you described.

I have found an issue:

The function board_qos_config() normally won't be entered unless ss_updown_db(SC_PGP_XXX, 0x1); is called.

(1) I speculate that the implementation of STC_RIL_SetInterleave is as follows:

void STC_RIL_SetInterleave(STC_Type *base, stc_interleave_mode_t interleave)
{
if (base == NULL ) {
return;
}

interleave &= 0x3;
base->INTERLEAVE_SEL = interleave;
}

After I used your code to disable the memory interleaving mode for 16 STC instances, I read the value of base->INTERLEAVE_SEL. Only subsystem 15 (base->INTERLEAVE_SEL=0x3) was set successfully. For the other subsystems, base->INTERLEAVE_SEL=0x0 failed to set, but base->RVSD_HPR_ENABLE=0x3. I don't know why it was set to RVSD_HPR_ENABLE. What is the relationship between INTERLEAVE_SEL and RVSD_HPR_ENABLE?

Could you please provide a manual describing the STC registers?

(2) When entering the board_qos_config(sc_sub_t ss) function, the value of ss is always 15. Does this mean only subsystem 15 can reconfigure the memory interleaving mode?

I am eagerly looking forward to your response!