topic NXP IMX8MP not receiving interrupts from ethernet phy in i.MX Processors

NXP IMX8MP not receiving interrupts from ethernet phy

Ben10 — Mon, 26 Feb 2024 12:24:54 GMT

We are using a custom board having NXP IMX8MP, developed based on the NXP IMX8MP EVK board. We are using the latest release of the Windows 10 IoT BSP. We have two ethernet ports which uses RTL8211FSI-VS-CG as the ethernet phy, the pin connections for both the ethernet phys with the SOC are same as the NXP IMX8MP EVK board. The first ethernet port supports ethernet QoS and it works correctly. The problem is with second ethernet port which doesn't support QoS, when we connect an ethernet cable to the ethernet port 2 and check the windows log, we observed that we are receiving the Tx interrupts, but we are not receiving the Rx interrupts. So, in the windows it shows as "connected no internet". So, what might be the problem and what are the possible solutions?

I have attached the windows logs for your reference.

Re: NXP IMX8MP not receiving interrupts from ethernet phy

hector_delgado — Mon, 26 Feb 2024 17:18:39 GMT

Hi @Ben10 ,

I hope you're doing well!

Can you please provide more details about the network environment you're testing both ethernet ports functionality? Are you using a testing tool such as iperf3?

Thank you.

Best regards,
Hector.

Re: NXP IMX8MP not receiving interrupts from ethernet phy

Ben10 — Tue, 27 Feb 2024 09:20:07 GMT

Hi @hector_delgado

Thanks for the reply. We are just doing a ping test as iperf3 doesn't run on windows 10 IoT. The problem we face is only with the second ethernet port. The difference between our board and the NXP IMX8MP EVK board, is our board uses RTL8211FSI-VS-CG as the ethernet phy while the NXP IMX8MP EVK board uses RTL8211FDI-CG as the ethernet phy. The pin connection between the ethernet phy and the SOC is the same for both the boards. When I connect an ethernet cable to the ethernet port 2 in our board, it shows as "connected no internet".

Re: NXP IMX8MP not receiving interrupts from ethernet phy

hector_delgado — Tue, 26 Mar 2024 17:27:00 GMT

Hi @Ben10 ,

I hope you're doing well and sorry for the late response.

it could be connected with RX/TX delay setting for ethernet PHY.

QoS Windows driver sets those delays in function MII_Rtl8211fInit in imx-windows-iot\driver\net\ndis\imxqosmini\mp_enet_phy.c.

NTSTATUS MII_Rtl8211fInit(PMP_ADAPTER pAdapter)
{
    NTSTATUS Status = STATUS_SUCCESS;
    UINT16 Val;
    UINT8 PhyAddr = pAdapter->MiiCfg.PhyAddr;

    // Select Page 0x0d08*/
    MII_Write(pAdapter, PhyAddr, 0x1F, 0x0d08);

    // Enable TX-delay for rgmii-id and rgmii-txid
    Val = MII_Read(pAdapter, PhyAddr, 0x11);
    if (pAdapter->MiiCfg.MiiInterfaceType == RGMII) {
        // RGMII config
        Val |= 0x0100;
    } else {
        Val &= ~0x0100;
    }
    MII_Write(pAdapter, PhyAddr, 0x11, Val);

    // Enable RX-delay for rgmii-id and rgmii-rxid
    Val = MII_Read(pAdapter, PhyAddr, 0x15);
    if (pAdapter->MiiCfg.MiiInterfaceType == RGMII) {
        // RGMII config
        Val |= 0x0008;
    } else {
        Val &= ~0x0008;
    }
    MII_Write(pAdapter, PhyAddr, 0x15, Val);

    // Restore to default page 0
    MII_Write(pAdapter, PhyAddr, 0x1F, 0x0000);

    // Set green LED for Link, yellow LED for Active
    MII_Write(pAdapter, PhyAddr, 0x1F, 0x0D04);
    MII_Write(pAdapter, PhyAddr, 0x10, 0x617F);
    MII_Write(pAdapter, PhyAddr, 0x1F, 0x0000);

    return Status;
}

But the other driver for ENET is using setting in ACPI table, which is for 8MP empty and thus it relays on PHY setting done in U-boot. ACPI table for i.MX93 have this setting filled and it can be used for 8MP:

mu_platform_nxp/NXP/MX93_11X11_EVK/AcpiTables/Dsdt-Enet.asl

Package (2) {"ConfigCmds", Package () {
                            MII_REG_WR (0x1F, 0x0d08),         // Select page
                            MII_REG_RMW(0x11, 0x0000, 0x0100), // Enable Tx-delay
                            MII_REG_RMW(0x15, 0x0000, 0x0008), // Enable Rx-delay
                            MII_REG_WR (0x1F, 0x0d04),         // Select page
                            MII_REG_WR (0x10, 0x617F),         // Set green LED for Link, yellow LED for Active
                            MII_REG_WR (0x1F, 0x0000),         // Set default page
                            ENET_MII_END}}

It can be put in mu_platform_nxp/NXP/MX8M_PLUS_EVK/AcpiTables/Dsdt-Enet.asl which it by default empty:

Package (2) {"ConfigCmds", Package () {
                            //  Enable GTX_CLK delay
                            //MII_WRITE_COMMAND(0x11, 0x0100),
                            //MII_WRITE_COMMAND(0x15, 0x0008),
                            ENET_MII_END}}

There is one difference, QoS driver have one line more there which is not in ACPI setting in i.MX93:

    // Restore to default page 0
    MII_Write(pAdapter, PhyAddr, 0x1F, 0x0000);

To have it same like QoS driver, I would add it there too:

Package (2) {"ConfigCmds", Package () {
                            MII_REG_WR (0x1F, 0x0d08),         // Select page
                            MII_REG_RMW(0x11, 0x0000, 0x0100), // Enable Tx-delay
                            MII_REG_RMW(0x15, 0x0000, 0x0008), // Enable Rx-delay
                            MII_REG_WR (0x1F, 0x0000),         // Set default page
                            MII_REG_WR (0x1F, 0x0d04),         // Select page
                            MII_REG_WR (0x10, 0x617F),         // Set green LED for Link, yellow LED for Active
                            MII_REG_WR (0x1F, 0x0000),         // Set default page
                            ENET_MII_END}}

Best regards,
Hector.

Re: NXP IMX8MP not receiving interrupts from ethernet phy

Ben10 — Wed, 27 Mar 2024 05:16:11 GMT

Hi @hector_delgado

We have already done what you have mentioned above, and the issue was fixed, but thanks anyways for the help and support.