<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: QSPI B Port data line issue in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-B-Port-data-line-issue/m-p/1811776#M220157</link>
    <description>&lt;P&gt;&amp;nbsp;Hi Aldo,&lt;/P&gt;&lt;P&gt;Thanks for your reply. How can we control this pinctrl-0 settings for both QSPI A as well as QSPI B.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_flexspi0&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;if you have any working device tree example related to QSPI port A as well QSPI port B&lt;/P&gt;&lt;P&gt;Please share with us.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Ramji Mishra&lt;/P&gt;</description>
    <pubDate>Tue, 20 Feb 2024 10:20:48 GMT</pubDate>
    <dc:creator>ramji1</dc:creator>
    <dc:date>2024-02-20T10:20:48Z</dc:date>
    <item>
      <title>QSPI B Port data line issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-B-Port-data-line-issue/m-p/1805896#M219920</link>
      <description>&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;I am using QSPI A and QSPI B both. One slave device is connect over QSPI A and&amp;nbsp; one slave device is connected over QSPI B. QSPI A port is working fine and QSPI B port is not working. we are not not able see any data over data line.&lt;/P&gt;&lt;P&gt;pinctrl_flexspi0: flexspi0grp {&lt;/P&gt;&lt;P&gt;fsl,pins = &amp;lt;&lt;BR /&gt;MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4&lt;BR /&gt;MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c4&lt;BR /&gt;MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x84&lt;BR /&gt;&amp;gt;;&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&amp;amp;flexspi {&lt;BR /&gt;pinctrl-names = "default";&lt;BR /&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_flexspi0&amp;gt;;&lt;BR /&gt;status = "okay";&lt;/P&gt;&lt;P&gt;w25Q01jvzeiq: flash@0 {&lt;BR /&gt;reg = &amp;lt;0&amp;gt;;&lt;BR /&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;compatible = "jedec,spi-nor";&lt;BR /&gt;spi-max-frequency = &amp;lt;80000000&amp;gt;;&lt;BR /&gt;spi-tx-bus-width = &amp;lt;4&amp;gt;;&lt;BR /&gt;spi-rx-bus-width = &amp;lt;4&amp;gt;;&lt;BR /&gt;partition@00000000 {&lt;BR /&gt;/* 1M for Uboot */&lt;BR /&gt;reg = &amp;lt;0x00000000 0x00200000&amp;gt;;&lt;BR /&gt;label = "qspi-uboot";&lt;BR /&gt;};&lt;BR /&gt;partition@1 {&lt;BR /&gt;/* 8M for kernel- zImage */&lt;BR /&gt;reg = &amp;lt;0x00200000 0x02000000&amp;gt;;&lt;BR /&gt;label = "kernel";&lt;BR /&gt;};&lt;BR /&gt;partition@2 {&lt;BR /&gt;/* 1M for device tree */&lt;BR /&gt;reg = &amp;lt;0x02300000 0x00100000&amp;gt;;&lt;BR /&gt;label = "dts";&lt;BR /&gt;};&lt;BR /&gt;partition@3 {&lt;BR /&gt;/* 20M for root file system */&lt;BR /&gt;reg = &amp;lt;0x02400000 0x01400000&amp;gt;;&lt;BR /&gt;label = "rootfs";&lt;BR /&gt;};&lt;BR /&gt;};&lt;BR /&gt;digitiser1: flash@2 {&lt;BR /&gt;reg = &amp;lt;2&amp;gt;;&lt;BR /&gt;compatible = "jedec,spi-nor";&lt;BR /&gt;spi-max-frequency = &amp;lt;10000000&amp;gt;;&lt;BR /&gt;spi-tx-bus-width = &amp;lt;4&amp;gt;;&lt;/P&gt;&lt;P&gt;spi-rx-bus-width = &amp;lt;4&amp;gt;;&lt;/P&gt;&lt;P&gt;We are using standard SPI nor driver.&lt;/P&gt;&lt;P&gt;Could you please guide us for this issue.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 13 Feb 2024 14:50:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-B-Port-data-line-issue/m-p/1805896#M219920</guid>
      <dc:creator>ramji1</dc:creator>
      <dc:date>2024-02-13T14:50:52Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI B Port data line issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-B-Port-data-line-issue/m-p/1811286#M220114</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Please try by separating the pad group for each of the devices, i.e.&lt;BR /&gt;&lt;BR /&gt;pinctrl_flexspi0: flexspi0grp {&lt;/P&gt;
&lt;P&gt;fsl,pins = &amp;lt;&lt;BR /&gt;MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4&lt;BR /&gt;MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84&lt;BR /&gt;&amp;gt;;&lt;BR /&gt;};&lt;/P&gt;
&lt;P&gt;pinctrl_flexspi1: flexspi1grp {&lt;/P&gt;
&lt;P&gt;fsl,pins = &amp;lt;&lt;BR /&gt;MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c4&lt;BR /&gt;MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x84&lt;BR /&gt;MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x84&lt;BR /&gt;&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;&lt;BR /&gt;Best regards/Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Mon, 19 Feb 2024 23:51:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-B-Port-data-line-issue/m-p/1811286#M220114</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2024-02-19T23:51:21Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI B Port data line issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-B-Port-data-line-issue/m-p/1811776#M220157</link>
      <description>&lt;P&gt;&amp;nbsp;Hi Aldo,&lt;/P&gt;&lt;P&gt;Thanks for your reply. How can we control this pinctrl-0 settings for both QSPI A as well as QSPI B.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_flexspi0&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;if you have any working device tree example related to QSPI port A as well QSPI port B&lt;/P&gt;&lt;P&gt;Please share with us.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Ramji Mishra&lt;/P&gt;</description>
      <pubDate>Tue, 20 Feb 2024 10:20:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-B-Port-data-line-issue/m-p/1811776#M220157</guid>
      <dc:creator>ramji1</dc:creator>
      <dc:date>2024-02-20T10:20:48Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI B Port data line issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-B-Port-data-line-issue/m-p/1814152#M220335</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;We do not have a sample device tree for this kind of use case, but you may use this one as an example:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi#L154" target="_blank"&gt;https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi#L154&lt;/A&gt;&lt;BR /&gt;&lt;A href="https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi#L95" target="_blank"&gt;https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi#L95&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;Best regards/Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Thu, 22 Feb 2024 23:27:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-B-Port-data-line-issue/m-p/1814152#M220335</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2024-02-22T23:27:52Z</dc:date>
    </item>
  </channel>
</rss>

