topic Required timing model (.v) for LPPDR4 simulation using Hyperlynx in i.MX Processors

Required timing model (.v) for LPPDR4 simulation using Hyperlynx

aprakashbaler — Mon, 12 Feb 2024 06:00:07 GMT

I am simulating for SI in hyperlinx for LPDDR4 interface at 4000mbits/s. there are failuers in max slew rate for all the drive strength and ODT configurations for Data write cycle.

Required timing model or any solution to reduce the slew rate.

Regards

Avinash B P

Re: Required timing model (.v) for LPPDR4 simulation using Hyperlynx

AldoG — Tue, 13 Feb 2024 16:29:40 GMT

Hello,

Could you share the device that you are testing?
Also, which verion of the IBIS file you are using?

Best regards/Saludos,
Aldo.

Re: Required timing model (.v) for LPPDR4 simulation using Hyperlynx

aprakashbaler — Wed, 14 Feb 2024 04:58:23 GMT

Hello Aldo,

Device i am using is MIMX8ML8CVNKZAB.

and the IBIS used is ibis_imx8mp_v2_20201023.

Regards

Avinash B P

Re: Required timing model (.v) for LPPDR4 simulation using Hyperlynx

AldoG — Thu, 29 Feb 2024 01:35:42 GMT

Hello,

max slew rate failures are not seen as a high risk. We recommend for customers follow our Hardware Developer's Guide and good design practices. And that should be enough.

Best regards/Saludos,
Aldo.