topic Re: Problems LPSPI on iMX8ULP in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/Problems-LPSPI-on-iMX8ULP/m-p/1804763#M219844 <P>Hi <a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/229326">@embeddedtom</a>!<BR />Thank you for contacting NXP Support!</P> <P>Try with the configuration below:</P> <P>&amp;lpspi4 {<BR />fsl,spi-num-chipselects = &lt;1&gt;;<BR />pinctrl-names = "default", "sleep";<BR />pinctrl-0 = &lt;&amp;pinctrl_lpspi4&gt;;<BR />pinctrl-1 = &lt;&amp;pinctrl_lpspi4&gt;;<BR />cs-gpios = &lt;&amp;gpiof 11 GPIO_ACTIVE_LOW&gt;;<BR />status = "okay";<BR /><BR />spidev0: spi@0 {<BR />reg = &lt;0&gt;;<BR />compatible = "lwn,bk4";<BR />spi-max-frequency = &lt;1000000&gt;;<BR />};<BR />};<BR /><BR />pinctrl_lpspi4: lpspi4grp {<BR />fsl,pins = &lt;<BR />MX8ULP_PAD_PTD20__LPSPI4_SIN&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0x43<BR />MX8ULP_PAD_PTD21__LPSPI4_SOUT&nbsp;&nbsp;&nbsp;&nbsp; 0x43<BR />MX8ULP_PAD_PTF10__LPSPI4_SCK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0x43<BR />MX8ULP_PAD_PTF11__PTF11&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0x43<BR />&gt;;<BR />};</P> <P>&nbsp;</P> <P>Best Regards!</P> <P>Chavira</P> Fri, 09 Feb 2024 15:50:39 GMT Chavira 2024-02-09T15:50:39Z Problems LPSPI on iMX8ULP https://community.nxp.com/t5/i-MX-Processors/Problems-LPSPI-on-iMX8ULP/m-p/1804592#M219833 <P>I'm trying to use LPSPI4 in my application. I took the following definitions from an example and transferred them to LPSPI4:</P><DIV>&amp;lpspi4 {</DIV><DIV><SPAN>fsl,spi-num-chipselects = &lt;1&gt;;</SPAN></DIV><DIV><SPAN>pinctrl-names = "default", "sleep";</SPAN></DIV><DIV><SPAN>pinctrl-0 = &lt;&amp;pinctrl_lpspi4&gt;;</SPAN></DIV><DIV><SPAN>pinctrl-1 = &lt;&amp;pinctrl_lpspi4&gt;;</SPAN></DIV><DIV>// cs-gpios = &lt;&amp;gpiof 19 GPIO_ACTIVE_LOW&gt;;</DIV><DIV>// pinctrl-assert-gpios = &lt;&amp;pca6416_1 10 GPIO_ACTIVE_LOW&gt;;</DIV><DIV><SPAN>status = "okay";</SPAN></DIV><DIV>&nbsp;</DIV><DIV><SPAN>spidev0: spi@0 {</SPAN></DIV><DIV><SPAN>reg = &lt;0&gt;;</SPAN></DIV><DIV><SPAN>compatible = "lwn,bk4";</SPAN></DIV><DIV><SPAN>spi-max-frequency = &lt;1000000&gt;;</SPAN></DIV><DIV><SPAN>};</SPAN></DIV><DIV>};</DIV><DIV>&nbsp;</DIV><DIV><DIV><SPAN>pinctrl_lpspi4: lpspi4grp {</SPAN></DIV><DIV><SPAN>fsl,pins = &lt;</SPAN></DIV><DIV><SPAN>MX8ULP_PAD_PTD20__LPSPI4_SIN 0x3</SPAN></DIV><DIV><SPAN>MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x3</SPAN></DIV><DIV><SPAN>MX8ULP_PAD_PTF10__LPSPI4_SCK 0x3</SPAN></DIV><DIV><SPAN>MX8ULP_PAD_PTF11__LPSPI4_PCS0 0x3</SPAN></DIV><DIV><SPAN>&gt;;</SPAN></DIV><DIV><SPAN>};</SPAN></DIV><DIV>&nbsp;</DIV><DIV><SPAN>Adding a UART worked, so in principle I should do it right, spidev0.0 now also exists in /dev, but all lines remain low during access. Would be very grateful for help!</SPAN></DIV></DIV> Fri, 09 Feb 2024 09:00:21 GMT https://community.nxp.com/t5/i-MX-Processors/Problems-LPSPI-on-iMX8ULP/m-p/1804592#M219833 embeddedtom 2024-02-09T09:00:21Z Re: Problems LPSPI on iMX8ULP https://community.nxp.com/t5/i-MX-Processors/Problems-LPSPI-on-iMX8ULP/m-p/1804763#M219844 <P>Hi <a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/229326">@embeddedtom</a>!<BR />Thank you for contacting NXP Support!</P> <P>Try with the configuration below:</P> <P>&amp;lpspi4 {<BR />fsl,spi-num-chipselects = &lt;1&gt;;<BR />pinctrl-names = "default", "sleep";<BR />pinctrl-0 = &lt;&amp;pinctrl_lpspi4&gt;;<BR />pinctrl-1 = &lt;&amp;pinctrl_lpspi4&gt;;<BR />cs-gpios = &lt;&amp;gpiof 11 GPIO_ACTIVE_LOW&gt;;<BR />status = "okay";<BR /><BR />spidev0: spi@0 {<BR />reg = &lt;0&gt;;<BR />compatible = "lwn,bk4";<BR />spi-max-frequency = &lt;1000000&gt;;<BR />};<BR />};<BR /><BR />pinctrl_lpspi4: lpspi4grp {<BR />fsl,pins = &lt;<BR />MX8ULP_PAD_PTD20__LPSPI4_SIN&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0x43<BR />MX8ULP_PAD_PTD21__LPSPI4_SOUT&nbsp;&nbsp;&nbsp;&nbsp; 0x43<BR />MX8ULP_PAD_PTF10__LPSPI4_SCK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0x43<BR />MX8ULP_PAD_PTF11__PTF11&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0x43<BR />&gt;;<BR />};</P> <P>&nbsp;</P> <P>Best Regards!</P> <P>Chavira</P> Fri, 09 Feb 2024 15:50:39 GMT https://community.nxp.com/t5/i-MX-Processors/Problems-LPSPI-on-iMX8ULP/m-p/1804763#M219844 Chavira 2024-02-09T15:50:39Z