https://community.nxp.com/t5/i-MX-Processors/SPI-Chip-Select-Behavior/m-p/1802837#M219722 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/196789">@moose</a>,&nbsp;</P> <P>Thank you for contacting NXP Support.</P> <P>No, that is not the expected behavior. I have tested on my side using the BSP version 6.1.55 and here are my results.</P> <P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="brian14_0-1707240417612.png" style="width: 718px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/262189iC7F298079C072BBC/image-dimensions/718x122?v=v2" width="718" height="122" role="button" title="brian14_0-1707240417612.png" alt="brian14_0-1707240417612.png" /></span></P> <P>Could you please tell me your BSP, your processor and if you are using an EVK or custom board?</P> Tue, 06 Feb 2024 17:27:17 GMT brian14 2024-02-06T17:27:17Z https://community.nxp.com/t5/i-MX-Processors/SPI-Chip-Select-Behavior/m-p/1801082#M219587 <P>Shouldn't chip select signal stay asserted for the entire transmission of a multi-byte frame? When I send an 8-byte frame, I see the CS go high after every byte, as shown below. Is this expected? Is there a way to configure it to stay asserted throughout the frame? I tried both spidev_test and spi-pip and experienced the same behavior. Below are the user space commands I tried. Any input? Thx!</P><P>`spidev_test -D /dev/spidev1.0 -v -p "\x55\x55\x55\x55\x00\x00\xff\xff"`</P><P>`printf '\x55\x55\x55\x55\x00\x00\xff\xff' | spi-pipe -d /dev/spidev1.0 --blocksize=8 | hexdump -C`</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="moose_0-1706903358685.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/261709i3E3AD850078AFB0A/image-size/medium?v=v2&amp;px=400" role="button" title="moose_0-1706903358685.png" alt="moose_0-1706903358685.png" /></span></P><P>CH1 (yellow) = SPI_CLK</P><P>CH2 (blue) = SPI_nCS</P><P>&nbsp;</P> Fri, 02 Feb 2024 19:52:23 GMT https://community.nxp.com/t5/i-MX-Processors/SPI-Chip-Select-Behavior/m-p/1801082#M219587 moose 2024-02-02T19:52:23Z https://community.nxp.com/t5/i-MX-Processors/SPI-Chip-Select-Behavior/m-p/1802837#M219722 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/196789">@moose</a>,&nbsp;</P> <P>Thank you for contacting NXP Support.</P> <P>No, that is not the expected behavior. I have tested on my side using the BSP version 6.1.55 and here are my results.</P> <P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="brian14_0-1707240417612.png" style="width: 718px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/262189iC7F298079C072BBC/image-dimensions/718x122?v=v2" width="718" height="122" role="button" title="brian14_0-1707240417612.png" alt="brian14_0-1707240417612.png" /></span></P> <P>Could you please tell me your BSP, your processor and if you are using an EVK or custom board?</P> Tue, 06 Feb 2024 17:27:17 GMT https://community.nxp.com/t5/i-MX-Processors/SPI-Chip-Select-Behavior/m-p/1802837#M219722 brian14 2024-02-06T17:27:17Z