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    <title>i.MX ProcessorsのトピックRe: Memory Map for i.MX RT1170 Processor</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1794822#M219165</link>
    <description>&lt;P&gt;Hello&lt;BR /&gt;I will gladly help you with these questions.&lt;/P&gt;
&lt;P&gt;1. This memory space is shared between cm7 and cm4 cores. The functionality is given by the specific application.&lt;BR /&gt;2. There are two OCRAMs(OCRAM1 and OCRAM2) of 512KB(if ECC is enabled otherwise it is 576KB). The mentioned OCRAM M7 is the FlexRAM, the size may vary according to the ITCM and DTCM sizes.&lt;BR /&gt;3. OCRAM1/2 are dedicated OCRAMS. OCRAMM7 is part of the FlexRAM and size can be relocated.&lt;BR /&gt;4. The NCACHE region is a portion of the external SDRAM that has non-cacheable attributes on the MPU.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Omar&lt;/P&gt;</description>
    <pubDate>Wed, 24 Jan 2024 18:41:36 GMT</pubDate>
    <dc:creator>Omar_Anguiano</dc:creator>
    <dc:date>2024-01-24T18:41:36Z</dc:date>
    <item>
      <title>Memory Map for i.MX RT1170 Processor</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1793368#M219043</link>
      <description>&lt;P&gt;This is the below Memory Map and IDE generated Linker script for the CM7 in i.MXRT1170:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="pk_23514_0-1705913394094.png" style="width: 622px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/259382i562FA6D8B76AFBAB/image-dimensions/622x126?v=v2" width="622" height="126" role="button" title="pk_23514_0-1705913394094.png" alt="pk_23514_0-1705913394094.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="pk_23514_0-1705977314051.png" style="width: 595px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/259519i89F3086060DA00FD/image-dimensions/595x195?v=v2" width="595" height="195" role="button" title="pk_23514_0-1705977314051.png" alt="pk_23514_0-1705977314051.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I have certain queries regarding the above images:&lt;/P&gt;&lt;P&gt;1. In the Linker script for CM7 generated by MCUExpresso, OCRAM M4 region is not mentioned although this memory region is accessible to CM7 processor? Is there any other functionality of this region except in the Dual boot process?&lt;BR /&gt;2. What is the complete OCRAM size for the Memory Map? Does it include all the sections mentioned above or only the OCRAM M7 and OCRAM defined in the FlexRAM region?&lt;BR /&gt;&lt;SPAN&gt;3. Is there any functionality difference between the OCRAM M7, OCRAM1 and OCRAM2?&lt;BR /&gt;4.&amp;nbsp;What is NCACHE region defined in the Linker script?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 23 Jan 2024 02:36:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1793368#M219043</guid>
      <dc:creator>pk_23514</dc:creator>
      <dc:date>2024-01-23T02:36:53Z</dc:date>
    </item>
    <item>
      <title>Re: Memory Map for i.MX RT1170 Processor</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1794822#M219165</link>
      <description>&lt;P&gt;Hello&lt;BR /&gt;I will gladly help you with these questions.&lt;/P&gt;
&lt;P&gt;1. This memory space is shared between cm7 and cm4 cores. The functionality is given by the specific application.&lt;BR /&gt;2. There are two OCRAMs(OCRAM1 and OCRAM2) of 512KB(if ECC is enabled otherwise it is 576KB). The mentioned OCRAM M7 is the FlexRAM, the size may vary according to the ITCM and DTCM sizes.&lt;BR /&gt;3. OCRAM1/2 are dedicated OCRAMS. OCRAMM7 is part of the FlexRAM and size can be relocated.&lt;BR /&gt;4. The NCACHE region is a portion of the external SDRAM that has non-cacheable attributes on the MPU.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Omar&lt;/P&gt;</description>
      <pubDate>Wed, 24 Jan 2024 18:41:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1794822#M219165</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2024-01-24T18:41:36Z</dc:date>
    </item>
    <item>
      <title>Re: Memory Map for i.MX RT1170 Processor</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1795317#M219199</link>
      <description>&lt;P&gt;Hello Omar,&lt;BR /&gt;Thanks for the response.&lt;/P&gt;&lt;P&gt;However, I still want to know the below points:&lt;BR /&gt;1. If OCRAM M4 region is shared between the CM7 and CM4 cores, so it&amp;nbsp;shall be &lt;STRONG&gt;defined in both the CM4 &amp;amp; CM7 Linker scripts&lt;/STRONG&gt; or &lt;STRONG&gt;any one of the CM4 or CM7 Linker script&lt;/STRONG&gt;?&lt;BR /&gt;2. So, the &lt;STRONG&gt;Total OCRAM size&lt;/STRONG&gt; = OCRAM configured in the FlexRAM (128kB to 640kB) + OCRMA1 (512kB to 576kB) + OCRAM2 (512kB to 576kB). Is this correct?&lt;BR /&gt;3.&amp;nbsp;Is the NCACHE region size fixed at 16 MB in the SEMC0 interfaced Memory? Or it can be of any size?&lt;/P&gt;&lt;P&gt;Thanks,&lt;BR /&gt;Prabhat Kiran.&lt;/P&gt;</description>
      <pubDate>Thu, 25 Jan 2024 09:42:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1795317#M219199</guid>
      <dc:creator>pk_23514</dc:creator>
      <dc:date>2024-01-25T09:42:37Z</dc:date>
    </item>
    <item>
      <title>Re: Memory Map for i.MX RT1170 Processor</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1799494#M219493</link>
      <description>&lt;P&gt;Hello Omar,&lt;/P&gt;&lt;P&gt;May I expect some response to the above queries at the earliest.&lt;BR /&gt;Appreciate your efforts.&lt;/P&gt;&lt;P&gt;Thanks,&lt;BR /&gt;Prabhat Kiran.&lt;/P&gt;</description>
      <pubDate>Thu, 01 Feb 2024 05:12:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1799494#M219493</guid>
      <dc:creator>pk_23514</dc:creator>
      <dc:date>2024-02-01T05:12:12Z</dc:date>
    </item>
    <item>
      <title>Re: Memory Map for i.MX RT1170 Processor</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1800246#M219542</link>
      <description>&lt;P&gt;I will gladly answer the other questions.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;1. It needs to be defined on both.&lt;BR /&gt;2. Correct.&lt;BR /&gt;3. It can be fixed to any size depending on your application.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Omar&lt;/P&gt;</description>
      <pubDate>Thu, 01 Feb 2024 19:57:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1800246#M219542</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2024-02-01T19:57:53Z</dc:date>
    </item>
    <item>
      <title>Re: Memory Map for i.MX RT1170 Processor</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1801550#M219626</link>
      <description>&lt;P&gt;Hello Omar,&lt;/P&gt;&lt;P&gt;Thanks for the response.&lt;BR /&gt;All the Memory segments and their implementation on the Linker script are clear.&lt;/P&gt;&lt;P&gt;Thanks,&lt;BR /&gt;Prabhat Kiran.&lt;/P&gt;</description>
      <pubDate>Mon, 05 Feb 2024 03:28:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1801550#M219626</guid>
      <dc:creator>pk_23514</dc:creator>
      <dc:date>2024-02-05T03:28:41Z</dc:date>
    </item>
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