https://community.nxp.com/t5/i-MX-Processors/LPDDR4-tDQSCK-timing/m-p/1784347#M218372 <P>Yes, you can use the <A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467" target="_blank">https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467</A> we supply.</P> Mon, 08 Jan 2024 10:08:20 GMT Rita_Wang 2024-01-08T10:08:20Z https://community.nxp.com/t5/i-MX-Processors/LPDDR4-tDQSCK-timing/m-p/1780685#M217961 <P>Hi NXP,</P><P>There is a timing tDQSCK involved in the read operation of the LPDDR4. Different LPDDR4 devices have different timing value.</P><P>Is it possible to get this value after the calibration is done? Ther target processor is i.MX8M Plus.</P><P>Thanks,</P><P>sng</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="simonng_0-1703731399559.png" style="width: 696px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/256090i24E695AF98DCFE40/image-dimensions/696x315?v=v2" width="696" height="315" role="button" title="simonng_0-1703731399559.png" alt="simonng_0-1703731399559.png" /></span></P><P>&nbsp;</P> Thu, 28 Dec 2023 02:47:47 GMT https://community.nxp.com/t5/i-MX-Processors/LPDDR4-tDQSCK-timing/m-p/1780685#M217961 simonng 2023-12-28T02:47:47Z https://community.nxp.com/t5/i-MX-Processors/LPDDR4-tDQSCK-timing/m-p/1784347#M218372 <P>Yes, you can use the <A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467" target="_blank">https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467</A> we supply.</P> Mon, 08 Jan 2024 10:08:20 GMT https://community.nxp.com/t5/i-MX-Processors/LPDDR4-tDQSCK-timing/m-p/1784347#M218372 Rita_Wang 2024-01-08T10:08:20Z