topic Re: i.MX8M+ eth vlan priority, queues & core isolation? in i.MX Processors

i.MX8M+ eth vlan priority, queues & core isolation?

dav1 — Mon, 02 Jan 2023 17:23:20 GMT

Trying to find more details around the frame classification (see from manual below)

Can I for instance filter so that time-sensitive ends up in its own buffer and IRQ,
thus allowing core-isolation so TSN/AVB traffic could be tied to the M7 while L3 traffic is passed to the A53?

Would also like some guidance to either code or more in-depth documentation for the two different PHY's in the imx8plus, there are obviously two variants of the IP's used for phy0 vs phy1. I'd like to understand
- what features are supported on each
- more details how fifo's/queues and irq's are segmented

thanks

Re: i.MX8M+ eth vlan priority, queues & core isolation?

jimmychan — Wed, 11 Jan 2023 03:04:23 GMT

There are two ethernet ports on i.MX8MP. One is normal ENET port, another one is EQOS which support TSN.

Two Ethernet controllers, capable of simultaneous operation
• One Gigabit Ethernet controller with support for EEE, Ethernet AVB and IEEE1588
• One Gigabit Ethernet controller with support for TSN, EEE, Ethernet AVB and IEEE1588

FYI. AVB/TSN demo.

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/AVB-TSN-demo-on-i-MX8MP/ta-p/1123791

GenAVB/TSN Stack Evaluation User Guide

https://www.nxp.com.cn/docs/en/user-guide/GENAVBTSNUG.pdf

Re: i.MX8M+ eth vlan priority, queues & core isolation?

dav1 — Mon, 30 Oct 2023 22:28:30 GMT

I noted in the gen avb examples, it seems hardcoded to use the software ptp rather than the hw feature in the 'tsn phy'. any plans to support both?

Re: i.MX8M+ eth vlan priority, queues & core isolation?

dav1 — Thu, 28 Dec 2023 20:45:48 GMT

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