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    <title>i.MX ProcessorsのトピックiMX8QM USB3 PHY register setups</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-USB3-PHY-register-setups/m-p/1779560#M217802</link>
    <description>&lt;P&gt;Hello all to whom it may concern,&lt;/P&gt;&lt;P&gt;I am currently designing the USB3 connection application based on iMX8QM host processor and have got substantially good results of phy characteristics&lt;BR /&gt;except tx eye opening, which is slightly cross the limit..&lt;/P&gt;&lt;P&gt;As far as I understand, the PCIe transceiver has some register to tune the voltage swing for adopting some application purpose (such as eye opening), and USB3 PIPE I/F have similar PHY structure so that it may be possible&lt;BR /&gt;to access and set the appropriate value for satisfying USB3 requirement.&lt;/P&gt;&lt;P&gt;Reviewing iMX8 Reference manual, I could not find any related results for the setup register especially TxMargin[2..0],TxSwing.&lt;/P&gt;&lt;P&gt;I am also trying to improve the artwork of USB differencial pair much more precisely, however does someone who knows about that more details of register setting for USB3?&lt;BR /&gt;Or is there any solution to improve the voltage swing for USB3 signal lane?&lt;/P&gt;&lt;P&gt;I am looking forward to see your comments, thank you very much in advance.&lt;/P&gt;</description>
    <pubDate>Mon, 25 Dec 2023 05:22:49 GMT</pubDate>
    <dc:creator>KT_tsuchida</dc:creator>
    <dc:date>2023-12-25T05:22:49Z</dc:date>
    <item>
      <title>iMX8QM USB3 PHY register setups</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-USB3-PHY-register-setups/m-p/1779560#M217802</link>
      <description>&lt;P&gt;Hello all to whom it may concern,&lt;/P&gt;&lt;P&gt;I am currently designing the USB3 connection application based on iMX8QM host processor and have got substantially good results of phy characteristics&lt;BR /&gt;except tx eye opening, which is slightly cross the limit..&lt;/P&gt;&lt;P&gt;As far as I understand, the PCIe transceiver has some register to tune the voltage swing for adopting some application purpose (such as eye opening), and USB3 PIPE I/F have similar PHY structure so that it may be possible&lt;BR /&gt;to access and set the appropriate value for satisfying USB3 requirement.&lt;/P&gt;&lt;P&gt;Reviewing iMX8 Reference manual, I could not find any related results for the setup register especially TxMargin[2..0],TxSwing.&lt;/P&gt;&lt;P&gt;I am also trying to improve the artwork of USB differencial pair much more precisely, however does someone who knows about that more details of register setting for USB3?&lt;BR /&gt;Or is there any solution to improve the voltage swing for USB3 signal lane?&lt;/P&gt;&lt;P&gt;I am looking forward to see your comments, thank you very much in advance.&lt;/P&gt;</description>
      <pubDate>Mon, 25 Dec 2023 05:22:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-USB3-PHY-register-setups/m-p/1779560#M217802</guid>
      <dc:creator>KT_tsuchida</dc:creator>
      <dc:date>2023-12-25T05:22:49Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8QM USB3 PHY register setups</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-USB3-PHY-register-setups/m-p/1780474#M217937</link>
      <description>&lt;P&gt;I have sent mail to you, pls check it&lt;/P&gt;</description>
      <pubDate>Wed, 27 Dec 2023 09:05:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-USB3-PHY-register-setups/m-p/1780474#M217937</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2023-12-27T09:05:28Z</dc:date>
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