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    <title>topic Interrupt for i.MX8M Mini in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Interrupt-for-i-MX8M-Mini/m-p/1779471#M217797</link>
    <description>&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Our customer need to use 8 IRQ (they planned to use IRQ56 ~ IRQ63) for external interrupt signals on i.MX8M Mini.&amp;nbsp;They designed PCB to use 4-11 of GPIO1, but they noticed that 0-7 of GPIO1 was fixed for interrupt.&amp;nbsp;Therefore, they can only use IRQ56-59 on their board&lt;SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Is there any way to support up to 8 interrupts from 4-11 of GPIO1 other than INT0-7?&lt;/P&gt;&lt;P&gt;In worst case scenario, customer is thinking of using the following IRQ 64.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;"Combined interrupt indication for GPIO1 signal 0 throughout 15"&lt;/P&gt;&lt;P&gt;In that case, is it possible to separate the operation of GPIO1&amp;nbsp; 4 - 7 and use only GPIO1&amp;nbsp; 8 - 11 to control IRQ64?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Thanks,&lt;/P&gt;&lt;P&gt;Norihiro Michigami&lt;/P&gt;&lt;P&gt;AVNET&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Sun, 24 Dec 2023 23:59:42 GMT</pubDate>
    <dc:creator>Norihiro</dc:creator>
    <dc:date>2023-12-24T23:59:42Z</dc:date>
    <item>
      <title>Interrupt for i.MX8M Mini</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interrupt-for-i-MX8M-Mini/m-p/1779471#M217797</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Our customer need to use 8 IRQ (they planned to use IRQ56 ~ IRQ63) for external interrupt signals on i.MX8M Mini.&amp;nbsp;They designed PCB to use 4-11 of GPIO1, but they noticed that 0-7 of GPIO1 was fixed for interrupt.&amp;nbsp;Therefore, they can only use IRQ56-59 on their board&lt;SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Is there any way to support up to 8 interrupts from 4-11 of GPIO1 other than INT0-7?&lt;/P&gt;&lt;P&gt;In worst case scenario, customer is thinking of using the following IRQ 64.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;"Combined interrupt indication for GPIO1 signal 0 throughout 15"&lt;/P&gt;&lt;P&gt;In that case, is it possible to separate the operation of GPIO1&amp;nbsp; 4 - 7 and use only GPIO1&amp;nbsp; 8 - 11 to control IRQ64?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Thanks,&lt;/P&gt;&lt;P&gt;Norihiro Michigami&lt;/P&gt;&lt;P&gt;AVNET&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 24 Dec 2023 23:59:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interrupt-for-i-MX8M-Mini/m-p/1779471#M217797</guid>
      <dc:creator>Norihiro</dc:creator>
      <dc:date>2023-12-24T23:59:42Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt for i.MX8M Mini</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interrupt-for-i-MX8M-Mini/m-p/1780110#M217885</link>
      <description>&lt;P&gt;FYI. Please read this thread for the gpio interrupt concept.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Interrupts-with-GPIO1-INT0-7/m-p/221515#M14660" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Interrupts-with-GPIO1-INT0-7/m-p/221515#M14660&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;And you can find the interrupt source by checking the GPIOx_ISR even the same group of gpio. Please read the chapter 8.3.2.3 Interrupt Control Unit in the RM for details.&lt;/P&gt;</description>
      <pubDate>Tue, 26 Dec 2023 16:48:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interrupt-for-i-MX8M-Mini/m-p/1780110#M217885</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2023-12-26T16:48:30Z</dc:date>
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