gicv3 interrupt init, interrupt trigger, interrupt handler at bl31 ATF ( EL3 mode )

dongjoo99kim — Thu, 07 Dec 2023 02:00:53 GMT

Dear all.

I have developed imx8mq including cortex a53, gicv3 controller.

As i know, bl31 in ATF can boot at EL3 mode, and bl31 in ATF can use fiq using gicv3.

If my understand is not correct, Please. correct me.

As i know, bl31 in ATF just use fiq triggered by other sw as like kernel ( non secure EL1 ) or Trust OS ( secure EL1 )

If my understand is not correct, Please. correct me.

I want to enable gicv3 interrupt init, interrupt trigger, interrupt handler at bl31 in ATF ( EL3 mode )

For example, after trigger interrupt at bl31 in ATF, I want to check the interrupt handler by bl31 exception vector table at bl31 in ATF.

I confuse the concept about irq and fiq.

Do the bl31 int ATF use only firq not irq ?

If bl31 in ATF use only firq, Could you share to me the method how to enable the fiq in bl31?

And, Could you share to me the method how to check the interrupt handler by bl31 exception vector table ?

If bl31 interrupt handler is triggered by bl31 exception vector table,

Could you share to me the location about bl31 exception vector table ?

Thanks.

Re: gicv3 interrupt init, interrupt trigger, interrupt handler at bl31 ATF ( EL3 mode )

Zhiming_Liu — Thu, 07 Dec 2023 02:31:24 GMT

Suggest you research the interrupt design in ATF: docs/design/interrupt-framework-design.rst

bl31/aarch64/runtime_exceptions.S

bl31/aarch64/bl31_entrypoint.S

el3_entrypoint_common \ _init_sctlr=1 \ _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ _init_memory=1 \ _init_c_runtime=1 \ _exception_vectors=runtime_exceptions \ _pie_fixup_size=BL31_LIMIT - BL31_BASE

i.MX Processorsのトピックgicv3 interrupt init, interrupt trigger, interrupt handler at bl31 ATF ( EL3 mode )

gicv3 interrupt init, interrupt trigger, interrupt handler at bl31 ATF ( EL3 mode )

Re: gicv3 interrupt init, interrupt trigger, interrupt handler at bl31 ATF ( EL3 mode )