adding ethernet controller

ilanganor1 — Mon, 04 Dec 2023 14:46:30 GMT

I am tryinh to add support for 2nd controlller as such, is it correct? is using fec is the correct way to go? are there missing things?:

+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy1>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "brcm,bcm54616S";
+ reg = <1>;
+ };
+ };
+};
+
+
+
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
@@ -782,6 +804,24 @@
>;
};

+ pinctrl_eqos1: eqosgrp1 {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x91
+ MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x91
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
+ MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
+ >;
+ };
+
+

Re: adding ethernet controller

JosephAtNXP — Tue, 05 Dec 2023 00:37:11 GMT

Hi,

Thank you for your interest in NXP Semiconductor products,

Based on I.MX 8M Plus EVK device tree and 8M Plus reference manual, I would make this observations.

+&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos1>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy1>; + status = "okay"; + + mdio { + #compatible = "snps,dwmac-mdio"; + + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "brcm,bcm54616S"; + reg = <1>; + }; + }; +}; + + + &flexspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi0>; @@ -782,6 +804,24 @@ >; }; + pinctrl_eqos1: eqosgrp1 { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 # 0x91 affects a reserved bit + MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 # Alt mode 1 + MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x11 + MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x11 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x11 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x11 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x11 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x11 + >; + }; + +

Regards

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adding ethernet controller

Re: adding ethernet controller