i.MX ProcessorsのトピックRe: IMX8 SPI chipselect stays active after transfer is complete

IMX8 SPI chipselect stays active after transfer is complete

nc87 — Thu, 16 Nov 2023 03:31:57 GMT

Hi,

I am facing an unusual issue with chipselect on ecspi2 staying active for an extended period of time even after transaction is complete.

This issue occurs on ecspi2 SPI controller talking to MCP2515 SPI device.

Here is my device tree

&ecspi2 {

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;

cs-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;

fsl,spi-num-chipselects = <1>;

status = "okay";

can1: can@0 {

compatible = "microchip,mcp2515";

//gpio-controller;

//#gpio-cells = <2>;

reg = <0>;

pinctrl-names = "default";

spi-max-frequency = <10000000>;

interrupt-parent = <&gpio5>;

interrupts = <21 IRQ_TYPE_LEVEL_LOW>;

clocks = <&can_osc_10m>;

};

Any suggestions as to what might be going on?

Thank You,

Naveen

Re: IMX8 SPI chipselect stays active after transfer is complete

AldoG — Tue, 21 Nov 2023 17:35:19 GMT

Hello,

Could you share the exact i.MX8 that you’re using for your test?
Also, which BSP version are you working with?

Saludos,
Aldo.

Re: IMX8 SPI chipselect stays active after transfer is complete

nc87 — Tue, 21 Nov 2023 19:32:56 GMT

Hi Aldo,

I am using IMX8MM with BSP-Yocto-NXP-i.MX8MM-PD22.1.0.

I came across an interesting observation - If I increase the CPU load or even shut off couple of cores this issue almost disappears. But we do need to get the bottom of this. Any help will be appreciated.

Thank You,

Naveen

Re: IMX8 SPI chipselect stays active after transfer is complete

AldoG — Wed, 22 Nov 2023 20:20:01 GMT

Hello,

This may be happening due to the module expect the TXFIFO to be filled to continue with the burst transfer.

This is configured in the ECSPIx_CONFIGREG(SS_CTL)[11-8], when set In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty.

Please refer to the reference manual chapter 10.1.2.4.1.3 Master Mode with SS_CTL[3:0] Control.

Best regards,
Aldo.