topic Re: IMX8MPLus HTXPHY_CLK_SEL source VPLL_PHY in i.MX Processors

IMX8MPLus HTXPHY_CLK_SEL source VPLL_PHY

jaylbrown — Tue, 18 Oct 2022 17:49:35 GMT

I would like to add spread spectrum to the iMX8MP HDMI pixel clock.

On page 5843 of the i.MX 8M Plus Applications Processor Reference Manual describes the HDMI_RTX_CLK_CTL1 Reg offset 50h bit 10 has HTXPHY_CLK_SEL.

It mentions VPLL_PHY as an alternative clock to drive INT_CLK input of PHY. The VPLL_PHY is not mentioned elsewhere in the manual.

Could someone please verity which clock VPLL_PHY is? Perhaps send me more detailed clock documentation describing the HDMI clock source.

My assumption is this is VIDEO_PLL1_OUT and INT_CLK is the HDMI TX PHY PLL reference clock for pixel clock generation.

Best Regards,

Jay

Re: IMX8MPLus HTXPHY_CLK_SEL source VPLL_PHY

Zhiming_Liu — Mon, 24 Oct 2022 02:25:04 GMT

Hi @jaylbrown

Please refer the Reference Manual.

The VPLL_PHY is an internal PLL module.

It mentions VPLL_PHY as an alternative clock to drive INT_CLK input of PHY.

-->correct

Re: IMX8MPLus HTXPHY_CLK_SEL source VPLL_PHY

jaylbrown — Thu, 27 Oct 2022 14:56:32 GMT

Hi @Zhiming_Liu Thanks for confirming VPLL_PHY = VIDEO_PLL1_OUT.

Re: IMX8MPLus HTXPHY_CLK_SEL source VPLL_PHY

jaylbrown — Mon, 20 Nov 2023 20:16:15 GMT

My apologies for a late update, but an NXP app engineer confirmed that the VPLL_PHY is not the VIDEO_PLL1_OUT.
It is an internal PHY test PLL that does not support spread spectrum.
Furthermore there is no clock path to achieve SS for HDMI.
We were able to reduce our EMI to pass compliance testing by modifying PHY LVDS drive parameters and termination resistance.

For our application, our HDMI EMI problem is solved.

Thanks, Jay